Abstract: Disclosed herein are quantum dot devices with trenched substrates, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate having a trench disposed therein, wherein a bottom of the trench is provided by a first material, and a quantum well stack at least partially disposed in the trench. A material of the quantum well stack may be in contact with the bottom of the trench, and the material of the quantum well stack may be different from the first material.

Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

Abstract: Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

Abstract: Disclosed herein are transistors with ferroelectric gates, and related methods and devices. For example, in some embodiments, a transistor may include a channel material, and a gate stack, and the gate stack may include a gate electrode material and a ferroelectric material between the gate electrode material and the channel material.

Abstract: An apparatus is formed. The apparatus includes a stack of semiconductor chips. The stack of semiconductor chips includes a logic chip and a memory stack, wherein, the logic chip includes at least one of a GPU and CPU. The apparatus also includes a semiconductor chip substrate. The stack of semiconductor chips are mounted on the semiconductor chip substrate. At least one other logic chip is mounted on the semiconductor chip substrate. The semiconductor chip substrate includes wiring to interconnect the stack of semiconductor chips to the at least one other logic chip.

Abstract: A semiconductor device comprising stacked complimentary transistors are described. In some embodiments, the semiconductor device comprises a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET), and a second device over the first device. In an example, the second device comprises a depletion mode thin film transistor. In an example, a connector is to couple a first terminal of the first device to a first terminal of the second device.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

Abstract: A method is described. The method includes forming bit line structures above bitline contact structures, forming a first material on top surfaces and sidewall surfaces of the bit line structures to establish step structures for via formation, and forming a second material on the top surface of the first material. Capacitor landing structures are formed by patterning the second material.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

Abstract: Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Abstract: An embodiment includes an apparatus comprising: a substrate; a thin film transistor (TFT) comprising: source, drain, and gate contacts; a semiconductor material, comprising a channel, between the substrate and the gate contact; a gate dielectric layer between the gate contact and the channel; and an additional layer between the channel and the substrate; wherein (a)(i) the channel includes carriers selected from the group consisting of hole carriers or electron carriers, (a)(ii) the additional layer includes an insulator material that includes charged particles having a polarity equal to a polarity of the carriers. Other embodiments are described herein.

Abstract: A thin film transistor (TFT) apparatus is disclosed, where the apparatus includes a gate comprising metal, a source and a drain, a semiconductor body, and two or more dielectric structures between the gate and the semiconductor body. In an example, the two or more dielectric structures may include at least a first dielectric structure having a first bandgap and a second dielectric structure having a second bandgap. The first bandgap may be different from the second bandgap. The TFT apparatus may be a back-gated TFT apparatus where the source is at least in part coplanar with the drain, and the gate is non-coplanar with the source and the drain.

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

Abstract: Described herein are integrated circuit devices with metal-oxide semiconductor channels and carbon source and drain (S/D) contacts. S/D contacts conduct current to and from the semiconductor devices, e.g., to the source and drain regions of a transistor. Carbon S/D contacts may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.

Abstract: Integrated circuit (IC) devices implementing pairs of thin-film transistors (TFTs) with shared contacts, and associated systems and methods, are disclosed. An example IC device may include a support structure, a channel layer provided over the support structure, where the channel layer includes a thin-film semiconductor material, a first TFT with a channel region that includes a first portion of the channel layer, and a second TFT with a channel region that includes a second portion of the channel layer. In some embodiments, a source or a drain (S/D) contact of the first TFT may be a shared contact that is also a S/D contact of the second TFT. In other embodiments, a gate contact/stack of the first TFT may be a shared contact/stack that is also a gate contact/stack of the second TFT.

Abstract: Techniques are provided for forming one or more thermoelectric devices integrated within a substrate of an integrated circuit. Backside substrate processing may be used to form adjacent portions of the substrate that are doped with alternating dopant types (e.g., n-type dopants alternating with p-type dopants). The substrate can then be etched to form pillars of the various n-type and p-type portions. Adjacent pillars of opposite dopant type can be electrically connected together via a conductive layer. Additionally, the top portions of adjacent pillars are connected together, and the bottom portions of a next pair of adjacent pillars being coupled together, in a repeating pattern to ensure that current flows through the length of each of the doped pillars. The flow of current through alternating n-type and p-type doped material creates a heat flux that transfers heat from one end of the integrated thermoelectric device to the other end.