Patents by Inventor Vibhor Jain

Vibhor Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HETEROJUNCTION BIPOLAR TRANSISTORS WITH UNDERCUT EXTRINSIC BASE REGIONS
    Publication number: 20220190145
    Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are positioned in a semiconductor substrate to define active regions. A base layer includes first sections that are respectively positioned over the active regions and second sections that are respectively positioned over the trench isolation regions. Emitter fingers are respectively positioned on the first sections of the base layer. The first sections of the base layer include single-crystal semiconductor material, and the second sections of the base layer include polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a first cavity that extends about a perimeter of the base layer and second cavities that are connected to the first cavity.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 16, 2022
    Inventors: Sarah McTaggart, Qizhi Liu, Vibhor Jain, Mark Levy, Paula Fisher, James R. Elliott
  • Heterojunction bipolar transistors with undercut extrinsic base regions
    Patent number: 11362201
    Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are positioned in a semiconductor substrate to define active regions. A base layer includes first sections that are respectively positioned over the active regions and second sections that are respectively positioned over the trench isolation regions. Emitter fingers are respectively positioned on the first sections of the base layer. The first sections of the base layer include single-crystal semiconductor material, and the second sections of the base layer include polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a first cavity that extends about a perimeter of the base layer and second cavities that are connected to the first cavity.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: June 14, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Sarah McTaggart, Qizhi Liu, Vibhor Jain, Mark Levy, Paula Fisher, James R. Elliott
  • Facilitating communications with automated assistants in multiple languages
    Patent number: 11354521
    Abstract: Techniques described herein relate to facilitating end-to-end multilingual communications with automated assistants. In various implementations, speech recognition output may be generated based on voice input in a first language. A first language intent may be identified based on the speech recognition output and fulfilled in order to generate a first natural language output candidate in the first language. At least part of the speech recognition output may be translated to a second language to generate an at least partial translation, which may then be used to identify a second language intent that is fulfilled to generate a second natural language output candidate in the second language. Scores may be determined for the first and second natural language output candidates, and based on the scores, a natural language output may be selected for presentation.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: June 7, 2022
    Assignee: GOOGLE LLC
    Inventors: James Kuczmarski, Vibhor Jain, Amarnag Subramanya, Nimesh Ranjan, Melvin Jose Johnson Premkumar, Vladimir Vuskovic, Luna Dai, Daisuke Ikeda, Nihal Sandeep Balani, Jinna Lei, Mengmeng Niu, Hongjie Chai, Wangqing Yuan
  • Chip package with emitter finger cells spaced by different spacings from a heat sink to provide reduced temperature variation
    Patent number: 11355409
    Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: June 7, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Hanyi Ding, Vibhor Jain, Alvin J. Joseph, Anthony K. Stamper
  • System and method for semantic analysis of song lyrics in a media content environment
    Patent number: 11354510
    Abstract: In accordance with an embodiment, described herein is a system and method for semantic analysis and use of song lyrics in a media content environment. Semantic analysis is used to identify persons, events, themes, stories, or other meaningful information within a plurality of songs. Example use cases include the selection and delivery of media content in response to input searches for songs of a particular nature; the recommendation or suggestion of media content in social messaging or other environments; or the delivery of an advertisement content based on a matching of song lyrics with advertisement topic words.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: June 7, 2022
    Assignee: Spotify AB
    Inventors: Ranqi Zhu, Minwei Gu, Vibhor Jain
  • METHOD AND RELATED STRUCTURE TO AUTHENTICATE INTEGRATED CIRCUIT WITH AUTHENTICATION FILM
    Publication number: 20220165676
    Abstract: The disclosure provides a method to authenticate an integrated circuit (IC) structure. The method may include forming a first authentication film (AF) material within the IC structure. A composition of the first AF material is different from an adjacent material within the IC structure. The method includes converting the first AF material into a void within the IC structure. Additionally, the method includes creating an authentication map of the IC structure to include a location of the void in the IC structure for authentication of the IC structure.
    Type: Application
    Filed: November 20, 2020
    Publication date: May 26, 2022
    Inventors: Vibhor Jain, Sunil K. Singh, Johnatan A. Kantarovsky, Siva P. Adusumilli, Sebastian T. Ventrone, John J. Ellis-Monaghan, Yves T. Ngu
  • NON-PLANAR SILICIDED SEMICONDUCTOR ELECTRICAL FUSE
    Publication number: 20220165663
    Abstract: An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 26, 2022
    Inventors: Ephrem G. Gebreselasie, Vibhor Jain, Yves T. Ngu, Johnatan A. Kantarovsky, Alain F. Loiseau
  • Boolean temperature sensing using phase transition material
    Patent number: 11333558
    Abstract: One device disclosed herein includes, among other things, a substrate, a first resistor comprising a first phase transition material formed above the substrate, the first phase transition material exhibiting a first dielectric phase for temperatures less than a first phase transition temperature and a first semiconductor phase for temperatures greater than the first phase transition temperature, and logic to detect a transition of the first resistor to the first semiconductor phase.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: May 17, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, Anthony K. Stamper, John J. Pekarik, Steven M. Shank
  • Avalanche photodiode
    Patent number: 11322639
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an avalanche photodiode and methods of manufacture. The structure includes: a substrate material having a trench with sidewalls and a bottom composed of the substrate material; a first semiconductor material lining the sidewalls and the bottom of the trench; a photosensitive semiconductor material provided on the first semiconductor material; and a third semiconductor material provided on the photosensitive semiconductor material.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: May 3, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Mark D. Levy, Siva P. Adusumilli, John J. Ellis-Monaghan, Vibhor Jain, Ramsey Hazbun, Pernell Dongmo, Cameron E. Luce, Steven M. Shank, Rajendran Krishnasamy
  • Electronic fuse (e-fuse) cells integrated with bipolar device
    Patent number: 11322497
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electronic fuse (e-fuse) cells integrated with a bipolar device and methods of manufacture. The structure includes: a bipolar device comprising a collector region, a base region and an emitter region; and an e-fuse integrated with and extending from the emitter region of the bipolar device.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: May 3, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Yves T. Ngu, Ephrem G. Gebreselasie, Vibhor Jain, Johnatan A. Kantarovsky
  • Photodiode and/or PIN diode structures
    Patent number: 11316064
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one fin including substrate material, the at least one fin including sidewalls and a top surface; a trench on opposing sides of the at least one fin; a first semiconductor material lining the sidewalls and the top surface of the at least one fin, and a bottom surface of the trench; a photosensitive semiconductor material on the first semiconductor material and at least partially filling the trench; and a third semiconductor material on the photosensitive semiconductor material.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 26, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Siva P. Adusumilli, John J. Ellis-Monaghan, Mark D. Levy, Vibhor Jain, Andre Sturm
  • HETEROJUNCTION BIPOLAR TRANSISTOR WITH BURIED TRAP RICH ISOLATION REGION
    Publication number: 20220123107
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: Vibhor JAIN, Anthony K. STAMPER, John J. ELLIS-MONAGHAN, Steven M. SHANK, Rajendran KRISHNASAMY
  • HETEROJUNCTION BIPOLAR TRANSISTOR WITH BURIED TRAP RICH ISOLATION REGION
    Publication number: 20220122968
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: Vibhor JAIN, John J. ELLIS-MONAGHAN, Anthony K. STAMPER, Steven M. SHANK, John J. PEKARIK
  • ANTI-TAMPER X-RAY BLOCKING PACKAGE
    Publication number: 20220115329
    Abstract: The present disclosure relates to integrated circuits, and more particularly, to an anti-tamper x-ray blocking package for secure integrated circuits and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: one or more devices on a front side of a semiconductor material; a plurality of patterned metal layers under the one or more devices, located and structured to protect the one or more devices from an active intrusion; an insulator layer between the plurality of patterned metal layers; and at least one contact providing an electrical connection through the semiconductor material to a front side of the plurality of metals.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 14, 2022
    Inventors: Johnatan A. KANTAROVSKY, Vibhor JAIN, Siva P. ADUSUMILLI, Ajay RAMAN, Sebastian T. VENTRONE, Yves T. NGU
  • Field effect transistors with back gate contact and buried high resistivity layer
    Patent number: 11296190
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors with back gate contact and buried high resistivity layer and methods of manufacture. The structure includes: a handle wafer comprising a single crystalline semiconductor region; an insulator layer over the single crystalline semiconductor region; a semiconductor layer over the insulator layer; a high resistivity layer in the handle wafer, separated from the insulator layer by the single crystalline semiconductor region; and a device on the semiconductor layer.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: April 5, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, Anthony K. Stamper, Steven M. Shank, John J. Ellis-Monaghan, John J. Pekarik
  • Trench-based photodiodes
    Patent number: 11282883
    Abstract: Structures including a photodiode and methods of fabricating such structures. A trench extends from a top surface of a substrate to a depth into the substrate. The photodiode includes an active layer positioned in the trench. Trench isolation regions, which are located in the substrate, are arranged to surround the trench. A portion of the substrate is positioned in a surrounding relationship about the active layer and between the active layer and the trench isolation regions.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 22, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: John J. Ellis-Monaghan, Steven M. Shank, Vibhor Jain, Anthony K. Stamper, John J. Pekarik
  • Wafer with crystalline silicon and trap rich polysilicon layer
    Patent number: 11271079
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wafer with crystalline silicon and trap rich polysilicon layer and methods of manufacture. The structure includes: semiconductor-on-insulator (SOI) wafer composed of a lower crystalline semiconductor layer, a polysilicon layer over the lower crystalline semiconductor layer, an upper crystalline semiconductor layer over the polysilicon layer, a buried insulator layer over the upper crystalline semiconductor layer, and a top crystalline semiconductor layer over the buried insulator layer.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: March 8, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anthony K. Stamper, Steven M. Shank, John J. Pekarik, Vibhor Jain, John J. Ellis-Monaghan
  • Trap-rich layer in a high-resistivity semiconductor layer
    Patent number: 11271077
    Abstract: Structures including electrical isolation and methods of forming a structure including electrical isolation. A semiconductor layer is formed over a semiconductor substrate and shallow trench isolation regions are formed in the semiconductor layer. The semiconductor layer includes single-crystal semiconductor material having an electrical resistivity that is greater than or equal to 1000 ohm-cm. The shallow trench isolation regions are arranged to surround a portion of the semiconductor layer to define an active device region. A polycrystalline layer is positioned in the semiconductor layer and extends laterally beneath the active device region and the shallow trench isolation regions that surround the active device region.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: March 8, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Anthony K. Stamper, Vibhor Jain, John J. Pekarik, Steven M. Shank, John J. Ellis-Monaghan
  • DEVICE COMPRISING AN OPTOFLUIDIC SENSOR WITH INTEGRATED PHOTODIODE
    Publication number: 20220062896
    Abstract: One illustrative device disclosed herein includes a semiconductor substrate, a channel that is at least partially defined by at least a portion of the semiconductor substrate, an input fluid reservoir and an output fluid reservoir, wherein the channel is in fluid communication with the input fluid reservoir and the output fluid reservoir. In this example, the device further includes a first radiation source operatively coupled to the substrate, wherein the first radiation source is adapted to generate radiation in a direction toward the channel, and at least one photodiode positioned adjacent the channel.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 3, 2022
    Inventors: Steven M. Shank, Vibhor Jain, Anthony Stamper, John Pekarik, John Ellis-Monaghan, Ramsey Hazbun
  • Transistor devices with source/drain regions comprising an interface layer that comprises a non-semiconductor material
    Patent number: 11264499
    Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and a source region and a drain region, each of which comprise an epi cavity with a bottom surface and a side surface. The transistor further includes an interface layer positioned on at least one of the side surface and the bottom surface of the epi cavity in each of the source/drain regions, wherein the interface layer comprises a non-semiconductor material and an epi semiconductor material positioned on at least an upper surface of the interface layer in the epi cavity in each of the source region and the drain region.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 1, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: John J. Pekarik, Steven M. Shank, Anthony K. Stamper, Vibhor Jain, John Ellis-Monaghan