Patents by Inventor Vibhor Jain

Vibhor Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TRAP-RICH LAYER IN A HIGH-RESISTIVITY SEMICONDUCTOR LAYER
    Publication number: 20210280672
    Abstract: Structures including electrical isolation and methods of forming a structure including electrical isolation. A semiconductor layer is formed over a semiconductor substrate and shallow trench isolation regions are formed in the semiconductor layer. The semiconductor layer includes single-crystal semiconductor material having an electrical resistivity that is greater than or equal to 1000 ohm-cm. The shallow trench isolation regions are arranged to surround a portion of the semiconductor layer to define an active device region. A polycrystalline layer is positioned in the semiconductor layer and extends laterally beneath the active device region and the shallow trench isolation regions that surround the active device region.
    Type: Application
    Filed: March 3, 2020
    Publication date: September 9, 2021
    Inventors: Anthony K. Stamper, Vibhor Jain, John J. Pekarik, Steven M. Shank, John J. Ellis-Monaghan
  • HETEROJUNCTION BIPOLAR TRANSISTORS WITH ONE OR MORE SEALED AIRGAP
    Publication number: 20210257454
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having one or more sealed airgap and methods of manufacture. The structure includes: a subcollector region in a substrate; a collector region above the substrate; a sealed airgap formed at least partly in the collector region; a base region adjacent to the collector region; and an emitter region adjacent to the base region.
    Type: Application
    Filed: February 14, 2020
    Publication date: August 19, 2021
    Inventors: Siva P. ADUSUMILLI, Rajendran KRISHNASAMY, Steven M. SHANK, Vibhor JAIN
  • Junction field effect transistor (JFET) structure and methods to form same
    Patent number: 11094834
    Abstract: A junction field effect transistor (JFET) structure includes a doped polysilicon gate over a channel region of a semiconductor layer. The doped polysilicon gate has a first doping type. A raised epitaxial source is on the source region of the semiconductor layer and adjacent a first sidewall of the doped polysilicon gate, and has a second doping type opposite the first doping type. A raised epitaxial drain is on the drain region of the semiconductor layer and adjacent a second sidewall of the doped polysilicon gate, and has the second doping type. A doped semiconductor region is within the channel region of the semiconductor layer and extending from the source region to the drain region, and a non-conductive portion of the semiconductor layer is within the channel region to separate the doped semiconductor region from the doped polysilicon gate.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: August 17, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Qizhi Liu, Vibhor Jain, John J. Pekarik, Judson R. Holt
  • HETEROJUNCTION BIPOLAR TRANSISTORS WITH STRESS MATERIAL FOR IMPROVED MOBILITY
    Publication number: 20210217874
    Abstract: According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a collector region, a base region formed on the collector region, and an emitter region formed on the base region. An isolation structure is formed in the substrate around the active device. A trench filled with a compressive material is formed in the substrate and positioned laterally adjacent to the emitter region and base region. The trench extends at least partially into the collector region.
    Type: Application
    Filed: March 29, 2021
    Publication date: July 15, 2021
    Applicant: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Anthony K. Stamper, Vibhor Jain, Renata A. Camillo-Castillo
  • WAFER WITH CRYSTALLINE SILICON AND TRAP RICH POLYSILICON LAYER
    Publication number: 20210217850
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wafer with crystalline silicon and trap rich polysilicon layer and methods of manufacture. The structure includes: semiconductor-on-insulator (SOI) wafer composed of a lower crystalline semiconductor layer, a polysilicon layer over the lower crystalline semiconductor layer, an upper crystalline semiconductor layer over the polysilicon layer, a buried insulator layer over the upper crystalline semiconductor layer, and a top crystalline semiconductor layer over the buried insulator layer.
    Type: Application
    Filed: January 15, 2020
    Publication date: July 15, 2021
    Inventors: Anthony K. STAMPER, Steven M. SHANK, John J. PEKARIK, Vibhor JAIN, John J. ELLIS-MONAGHAN
  • FIELD EFFECT TRANSISTORS WITH BACK GATE CONTACT AND BURIED HIGH RESISTIVITY LAYER
    Publication number: 20210217849
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors with back gate contact and buried high resistivity layer and methods of manufacture. The structure includes: a handle wafer comprising a single crystalline semiconductor region; an insulator layer over the single crystalline semiconductor region; a semiconductor layer over the insulator layer; a high resistivity layer in the handle wafer, separated from the insulator layer by the single crystalline semiconductor region; and a device on the semiconductor layer.
    Type: Application
    Filed: January 15, 2020
    Publication date: July 15, 2021
    Inventors: Vibhor JAIN, Anthony K. STAMPER, Steven M. SHANK, John J. ELLIS-MONAGHAN, John J. PEKARIK
  • Complementary transistor structures formed with the assistance of doped-glass layers
    Patent number: 11063140
    Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: July 13, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: John J. Pekarik, Anthony K. Stamper, Vibhor Jain, Steven M. Shank, John J. Ellis-Monaghan, Herbert Ho, Qizhi Liu
  • Heterojunction bipolar transistors with airgap isolation
    Patent number: 11063139
    Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A collector layer includes an inclined side surface, and a dielectric layer is positioned in a lateral direction adjacent to the inclined side surface of the collector layer. An intrinsic base is disposed over the collector layer, and an emitter is disposed over the intrinsic base. An airgap is positioned between the dielectric layer and the inclined side surface of the collector layer in the lateral direction, and an extrinsic base is positioned in the lateral direction adjacent to the intrinsic base. The extrinsic base is positioned over the airgap.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: July 13, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, John J. Pekarik, Qizhi Liu, Judson Holt
  • FACILITATING END-TO-END COMMUNICATIONS WITH AUTOMATED ASSISTANTS IN MULTIPLE LANGUAGES
    Publication number: 20210210076
    Abstract: Techniques described herein relate to facilitating end-to-end multilingual communications with automated assistants. In various implementations, speech recognition output may be generated based on voice input in a first language. A first language intent may be identified based on the speech recognition output and fulfilled in order to generate a first natural language output candidate in the first language. At least part of the speech recognition output may be translated to a second language to generate an at least partial translation, which may then be used to identify a second language intent that is fulfilled to generate a second natural language output candidate in the second language. Scores may be determined for the first and second natural language output candidates, and based on the scores, a natural language output may be selected for presentation.
    Type: Application
    Filed: March 24, 2021
    Publication date: July 8, 2021
    Inventors: James Kuczmarski, Vibhor Jain, Amarnag Subramanya, Nimesh Ranjan, Melvin Jose Johnson Premkumar, Vladimir Vuskovic, Luna Dai, Daisuke Ikeda, Nihal Sandeep Balani, Jinna Lei, Mengmeng Niu
  • TRANSISTORS WITH LATTICE STRUCTURE
    Publication number: 20210202717
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with an oxygen lattice structure and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the substrate; at least one oxygen film separating the sub-collector region and the collector region; an emitter region adjacent to the collector region; and a base region adjacent to the emitter region.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Inventors: Vibhor JAIN, Steven M. SHANK, John J. PEKARIK, Anthony K. STAMPER
  • TRENCH-BASED PHOTODIODES
    Publication number: 20210183918
    Abstract: Structures including a photodiode and methods of fabricating such structures. A trench extends from a top surface of a substrate to a depth into the substrate. The photodiode includes an active layer positioned in the trench. Trench isolation regions, which are located in the substrate, are arranged to surround the trench. A portion of the substrate is positioned in a surrounding relationship about the active layer and between the active layer and the trench isolation regions.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: John J. Ellis-Monaghan, Steven M. Shank, Vibhor Jain, Anthony K. Stamper, John J. Pekarik
  • Sensors with a front-end-of-line solution-receiving cavity
    Patent number: 11016055
    Abstract: Structures for transistor-based sensors and related fabrication methods. A layer stack is formed that includes a semiconductor layer and a cavity. A transistor is formed that has a gate electrode over the layer stack, and an interconnect structure is formed over the layer stack and the transistor. First and second openings are formed that extend through the metallization levels of the interconnect structure and the semiconductor layer to the cavity. The first opening defines a fluid inlet coupled to the cavity, and the second opening defines a fluid outlet coupled to the cavity.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 25, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Humberto Campanella-Pineda, Qizhi Liu, Vibhor Jain, You Qian, Joan Josep Giner de Haro
  • PHOTODETECTORS WITH A LATERAL COMPOSITION GRADIENT
    Publication number: 20210151621
    Abstract: Structures including a photodetector and methods of fabricating such structures. The photodetector is positioned over the top surface of the substrate. The photodetector includes a portion of a semiconductor layer comprised of a semiconductor alloy, a p-type doped region in the portion of the semiconductor layer, and an n-type doped region in the portion of the semiconductor layer. The p-type doped region and the n-type doped region converge along a p-n junction. The portion of the semiconductor layer has a first side and a second side opposite from the first side. The semiconductor alloy has a composition that is laterally graded from the first side to the second side of the portion of the semiconductor layer.
    Type: Application
    Filed: November 18, 2019
    Publication date: May 20, 2021
    Inventors: Steven M. Shank, Vibhor Jain, Anthony K. Stamper, John J. Ellis-Monaghan, John J. Pekarik
  • Photodiodes integrated into a BiCMOS process
    Patent number: 11004878
    Abstract: Structures including a photodiode and methods of fabricating such structures. A substrate has a top surface, a well, and a trench extending from the top surface to the well. A photodiode is positioned in the trench. The photodiode includes an electrode that is provided by a first portion of the well. A bipolar junction transistor has an emitter that is positioned over the top surface of the substrate and a subcollector that is positioned below the top surface of the substrate. The subcollector is provided by a second portion of the well.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: May 11, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anthony K. Stamper, Vibhor Jain, Steven M. Shank, John J. Ellis-Monaghan, John J. Pekarik
  • SILICON PHOTONIC COMPONENTS FABRICATED USING A BULK SUBSTRATE
    Publication number: 20210132461
    Abstract: Structures including a photodetector and methods of fabricating such structures. A substrate, which is composed of a semiconductor material, includes a first trench, a second trench, and a pillar of the semiconductor material that is laterally positioned between the first trench and the second trench. A first portion of a dielectric layer is located in the first trench and a second portion of the dielectric layer is located in the second trench. A waveguide core is coupled to the pillar at a top surface of the substrate.
    Type: Application
    Filed: November 5, 2019
    Publication date: May 6, 2021
    Inventors: Vibhor Jain, Siva P. Adusumilli, John J. Ellis-Monaghan
  • Silicon photonic components fabricated using a bulk substrate
    Patent number: 10983412
    Abstract: Structures including a photodetector and methods of fabricating such structures. A substrate, which is composed of a semiconductor material, includes a first trench, a second trench, and a pillar of the semiconductor material that is laterally positioned between the first trench and the second trench. A first portion of a dielectric layer is located in the first trench and a second portion of the dielectric layer is located in the second trench. A waveguide core is coupled to the pillar at a top surface of the substrate.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: April 20, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, Siva P. Adusumilli, John J. Ellis-Monaghan
  • Facilitating end-to-end communications with automated assistants in multiple languages
    Patent number: 10984784
    Abstract: Techniques described herein relate to facilitating end-to-end multilingual communications with automated assistants. In various implementations, speech recognition output may be generated based on voice input in a first language. A first language intent may be identified based on the speech recognition output and fulfilled in order to generate a first natural language output candidate in the first language. At least part of the speech recognition output may be translated to a second language to generate an at least partial translation, which may then be used to identify a second language intent that is fulfilled to generate a second natural language output candidate in the second language. Scores may be determined for the first and second natural language output candidates, and based on the scores, a natural language output may be selected for presentation.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: April 20, 2021
    Assignee: GOOGLE LLC
    Inventors: James Kuczmarski, Vibhor Jain, Amarnag Subramanya, Nimesh Ranjan, Melvin Jose Johnson Premkumar, Vladimir Vuskovic, Luna Dai, Daisuke Ikeda, Nihal Sandeep Balani, Jinna Lei, Mengmeng Niu
  • DOUBLE MESA HETEROJUNCTION BIPOLAR TRANSISTOR
    Publication number: 20210111247
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base region composed of intrinsic base material located above the collector region; an emitter located above and separated from the intrinsic base material; and a raised extrinsic base having a stepped configuration and separated from and self-aligned to the emitter.
    Type: Application
    Filed: February 28, 2020
    Publication date: April 15, 2021
    Inventors: John J. PEKARIK, Vibhor JAIN
  • HETEROJUNCTION BIPOLAR TRANSISTOR WITH EMITTER BASE JUNCTION OXIDE INTERFACE
    Publication number: 20210104621
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.
    Type: Application
    Filed: December 16, 2020
    Publication date: April 8, 2021
    Inventors: Vibhor JAIN, Anthony K. STAMPER, Steven M. SHANK, John J. PEKARIK
  • Self-aligned base and emitter for a bipolar junction transistor
    Patent number: 10971597
    Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer includes a first section and a second section that are located over the active region. An emitter is positioned on the first section of the base layer, and an extrinsic base layer is positioned on the second section of the base layer. The extrinsic base layer has a side surface adjacent to the emitter. The side surface of the extrinsic base layer is inclined relative to a top surface of the base layer in a direction away from the emitter.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: April 6, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Qizhi Liu, Vibhor Jain, John J. Pekarik