Patents by Inventor Vibhor Jain

Vibhor Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • III-V COMPOUND SEMICONDUCTOR LAYER STACKS WITH ELECTRICAL ISOLATION PROVIDED BY A TRAP-RICH LAYER
    Publication number: 20220029000
    Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. A layer stack is formed on a semiconductor substrate comprised of a single-crystal semiconductor material. The layer stack includes a semiconductor layer comprised of a III-V compound semiconductor material. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer extends laterally beneath the layer stack.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 27, 2022
    Inventors: Anthony K. Stamper, Siva P. Adusumilli, Vibhor Jain, Steven Bentley
  • Heterojunction bipolar transistor with marker layer
    Patent number: 11217685
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a marker layer and methods of manufacture. The device includes: a collector region; an intrinsic base region above the collector region; an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material; and an extrinsic base region in electrical contact with the intrinsic base region.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: January 4, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Herbert Ho, Vibhor Jain, John J. Pekarik, Claude Ortolland, Judson R. Holt, Qizhi Liu, Viorel Ontalus
  • DOUBLE MESA HETEROJUNCTION BIPOLAR TRANSISTOR
    Publication number: 20210408238
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base region composed of intrinsic base material located above the collector region; an emitter located above and separated from the intrinsic base material; and a raised extrinsic base having a stepped configuration and separated from and self-aligned to the emitter.
    Type: Application
    Filed: September 13, 2021
    Publication date: December 30, 2021
    Inventors: John J. PEKARIK, Vibhor JAIN
  • PHOTODIODE AND/OR PIN DIODE STRUCTURES
    Publication number: 20210391489
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one vertical pillar feature within a trench; a photosensitive semiconductor material extending laterally from sidewalls of the at least one vertical pillar feature; and a contact electrically connecting to the photosensitive semiconductor material.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 16, 2021
    Inventors: Mark D. LEVY, Siva P. ADUSUMILLI, Vibhor JAIN, John J. ELLIS-MONAGHAN
  • Heterojunction bipolar transistors
    Patent number: 11195925
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the sub-collector region, the collector region composed of semiconductor material; an intrinsic base region composed of intrinsic base material surrounded by the semiconductor material above the collector region; and an emitter region above the intrinsic base region.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: December 7, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Judson R. Holt, Vibhor Jain, Qizhi Liu, Ramsey Hazbun, Pernell Dongmo, John J. Pekarik, Cameron E. Luce
  • PHOTODIODE AND/OR PIN DIODE STRUCTURES
    Publication number: 20210376180
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one fin including substrate material, the at least one fin including sidewalls and a top surface; a trench on opposing sides of the at least one fin; a first semiconductor material lining the sidewalls and the top surface of the at least one fin, and a bottom surface of the trench; a photosensitive semiconductor material on the first semiconductor material and at least partially filling the trench; and a third semiconductor material on the photosensitive semiconductor material.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Inventors: Siva P. ADUSUMILLI, John J. ELLIS-MONAGHAN, Mark D. LEVY, Vibhor JAIN, Andre STURM
  • Heterojunction bipolar transistor
    Patent number: 11177347
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes a collector region composed of semiconductor material; at least one marker layer over the collector region; a layer of doped semiconductor material which forms an extrinsic base and which is located above the at least one marker layer; a cavity formed in the layer of doped semiconductor material and extending at least to the at least one marker layer; an epitaxial intrinsic base layer of doped material located within the cavity; and an emitter material over the epitaxial intrinsic base layer and within an opening formed by sidewall spacer structures.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: November 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Judson R. Holt, Vibhor Jain, Qizhi Liu, John J. Pekarik
  • PHOTODETECTOR WITH REFLECTOR WITH AIR GAP ADJACENT PHOTODETECTING REGION
    Publication number: 20210351306
    Abstract: A photodetector includes a photodetecting region in a semiconductor substrate, and a reflector extending at least partially along a sidewall of the photodetecting region in the semiconductor substrate. The reflector includes an air gap defined in the semiconductor substrate. The reflector allows use of thinner germanium for the photodetecting region. The air gap may have a variety of internal features to direct electromagnetic radiation towards the photodetecting region.
    Type: Application
    Filed: May 7, 2020
    Publication date: November 11, 2021
    Inventors: Siva P. Adusumilli, Mark D. Levy, Vibhor Jain, John J. Ellis-Monaghan
  • Double mesa heterojunction bipolar transistor
    Patent number: 11171210
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base region composed of intrinsic base material located above the collector region; an emitter located above and separated from the intrinsic base material; and a raised extrinsic base having a stepped configuration and separated from and self-aligned to the emitter.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: November 9, 2021
    Assignee: GLOBALPOUNDRIES U.S. INC.
    Inventors: John J. Pekarik, Vibhor Jain
  • Active attack prevention for secure integrated circuits using latchup sensitive diode circuit
    Patent number: 11171095
    Abstract: The present disclosure relates to an active x-ray attack prevention structure for secure integrated circuits. In particular, the present disclosure relates to a structure including a functional circuit, and at least one latchup sensitive diode circuit configured to induce a latchup condition in the functional circuit, placed in proximity of the functional circuit.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: November 9, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, Ajay Raman, Sebastian T. Ventrone, John J. Ellis-Monaghan, Siva P. Adusumilli, Yves T. Ngu
  • ACTIVE ATTACK PREVENTION FOR SECURE INTEGRATED CIRCUITS USING LATCHUP SENSITIVE DIODE CIRCUIT
    Publication number: 20210335731
    Abstract: The present disclosure relates to an active x-ray attack prevention structure for secure integrated circuits. In particular, the present disclosure relates to a structure including a functional circuit, and at least one latchup sensitive diode circuit configured to induce a latchup condition in the functional circuit, placed in proximity of the functional circuit.
    Type: Application
    Filed: April 22, 2020
    Publication date: October 28, 2021
    Inventors: Vibhor JAIN, Ajay RAMAN, Sebastian T. VENTRONE, John J. ELLIS-MONAGHAN, Siva P. ADUSUMILLI, Yves T. NGU
  • FIELD EFFECT TRANSISTOR (FET) STACK AND METHODS TO FORM SAME
    Publication number: 20210336005
    Abstract: The disclosure provides a field effect transistor (FET) stack with methods to form the same. The FET stack includes a first transistor over a substrate. The first transistor includes a first active semiconductor material including a first channel region between a first set of source/drain terminals, and a first gate structure over the first channel region. The first gate structure includes a first gate insulator of a first thickness above the first channel region. A second transistor is over the substrate and horizontally separated from the first transistor. A second gate structure of the second transistor may include a second gate insulator of a second thickness above a second channel region, the second thickness being greater than the first thickness. A shared gate node may be coupled to each of the first gate structure and the second gate structure.
    Type: Application
    Filed: April 22, 2020
    Publication date: October 28, 2021
    Inventors: Steven M. Shank, Anthony K. Stamper, Vibhor Jain, John J. Ellis-Monaghan
  • Transistors with lattice structure
    Patent number: 11158722
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with an oxygen lattice structure and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the substrate; at least one oxygen film separating the sub-collector region and the collector region; an emitter region adjacent to the collector region; and a base region adjacent to the emitter region.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 26, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, Steven M. Shank, John J. Pekarik, Anthony K. Stamper
  • Photodetector with reflector with air gap adjacent photodetecting region
    Patent number: 11152520
    Abstract: A photodetector includes a photodetecting region in a semiconductor substrate, and a reflector extending at least partially along a sidewall of the photodetecting region in the semiconductor substrate. The reflector includes an air gap defined in the semiconductor substrate. The reflector allows use of thinner germanium for the photodetecting region. The air gap may have a variety of internal features to direct electromagnetic radiation towards the photodetecting region.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: October 19, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Siva P. Adusumilli, Mark D. Levy, Vibhor Jain, John J. Ellis-Monaghan
  • AVALANCHE PHOTODIODE
    Publication number: 20210320217
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an avalanche photodiode and methods of manufacture. The structure includes: a substrate material having a trench with sidewalls and a bottom composed of the substrate material; a first semiconductor material lining the sidewalls and the bottom of the trench; a photosensitive semiconductor material provided on the first semiconductor material; and a third semiconductor material provided on the photosensitive semiconductor material.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Inventors: Mark D. LEVY, Siva P. ADUSUMILLI, John J. ELLIS-MONAGHAN, Vibhor JAIN, Ramsey HAZBUN, Pernell DONGMO, Cameron E. LUCE, Steven M. SHANK, Rajendran KRISHNASAMY
  • Heterojunction bipolar transistor
    Patent number: 11145725
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region in electrical connection to the sub-collector region; an emitter located adjacent to the collector region and comprising emitter material, recessed sidewalls on the emitter material and an extension region extending at an upper portion of the emitter material above the recessed sidewalls; and an extrinsic base separated from the emitter by the recessed sidewalls.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: October 12, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Qizhi Liu, Vibhor Jain, Judson R. Holt, Herbert Ho, Claude Ortolland, John J. Pekarik
  • PHOTODETECTOR WITH BURIED AIRGAP REFLECTORS
    Publication number: 20210313373
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.
    Type: Application
    Filed: April 7, 2020
    Publication date: October 7, 2021
    Inventors: Siva P. ADUSUMILLI, Vibhor JAIN, Alvin J. JOSEPH, Steven M. SHANK
  • Transistor structure with overlying gate on polysilicon gate structure and related method
    Patent number: 11127831
    Abstract: Embodiments of the disclosure provide a transistor structure and methods to form the same. The transistor structure may include an active semiconductor region with a channel region between a first source/drain (S/D) region and a second S/D region. A polysilicon gate structure is above the channel region of the active semiconductor region. An overlying gate is positioned on the polysilicon gate structure. A horizontal width of the overlying gate is greater than a horizontal width of the polysilicon gate structure. The transistor structure includes a gate contact to the overlying gate.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: September 21, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Qizhi Liu, Vibhor Jain, John J. Pekarik, Judson R. Holt
  • Heterojunction bipolar transistors with one or more sealed airgap
    Patent number: 11127816
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having one or more sealed airgap and methods of manufacture. The structure includes: a subcollector region in a substrate; a collector region above the substrate; a sealed airgap formed at least partly in the collector region; a base region adjacent to the collector region; and an emitter region adjacent to the base region.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: September 21, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Siva P. Adusumilli, Rajendran Krishnasamy, Steven M. Shank, Vibhor Jain
  • Active x-ray attack prevention device
    Patent number: 11121097
    Abstract: The present disclosure relates to a metal layer for an active x-ray attack prevention device for securing integrated circuits. In particular, the present disclosure relates to a structure including a semiconductor material, one or more devices on a front side of the semiconductor material, a backside patterned metal layer under the one or more devices, located and structured to protect the one or more devices from an active intrusion, and at least one contact providing an electrical connection through the semiconductor material to a front side of the backside patterned metal layer. The backside patterned metal layer is between a wafer and one of the semiconductor material and an insulator layer.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: September 14, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, Sebastian T. Ventrone, Siva P. Adusumilli, John J. Ellis-Monaghan, Ajay Raman