Patents by Inventor Vijay Raghavan

Vijay Raghavan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11956483
    Abstract: An embodiment of a digital content distribution system for a delivery of digital materials through digital mailbox systems is described. The digital content distribution system features a virtual processor and a plurality of digital mailbox systems. Each digital mailbox system is configured to operate as a data store addressable by a digital mailbox address that is uniquely associated with a physical address and is assigned to one or more registered users associated with a property identified by the physical address. For instance, a first digital mailbox system is configured to transmit digital materials to and receive digital materials from a second digital mailbox system different than the first digital mailbox system and one or more registered users are provided access to the digital materials received by the first digital mailbox system upon authentication.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: April 9, 2024
    Assignee: Digital Mailbox, Inc.
    Inventor: Vijay Raghavan Chetty
  • Patent number: 11917601
    Abstract: A method of wireless communication includes receiving a first beam using a first antenna device during an occasion of a reference signal. The method further includes receiving a second beam using a second antenna device that is distinct from the first antenna device during the occasion of the reference signal. Receiving the first beam and the second beam includes inputting, to a modem, a representation of a combination of the first beam and the second beam. Receiving the first beam and the second beam further includes generating, by the modem based on the representation, a first signal associated with the first beam using a first parameter associated with the first antenna device and a second signal associated with the second beam using a second parameter associated with the second antenna device.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: February 27, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Mihir Vijay Laghate, Revathi Sundara Raghavan, Bhushan Shanti Asuri
  • Publication number: 20230259748
    Abstract: A method of operation of a semiconductor device that includes the steps of coupling each of a plurality of digital inputs to a corresponding row of non-volatile memory (NVM) cells that stores an individual weight, initiating a read operation based on a digital value of a first bit of the plurality of digital inputs, accumulating along a first bit-line coupling a first array column weighted bit-line current, in which the weighted bit-line current corresponds to a product of the individual weight stored therein and the digital value of the first bit, and converting and scaling, an accumulated weighted bit-line current of the first column, into a scaled charge of the first bit in relation to a significance of the first bit.
    Type: Application
    Filed: February 17, 2023
    Publication date: August 17, 2023
    Applicant: Infineon Technologies LLC
    Inventors: Ramesh CHETTUVETTY, Vijay RAGHAVAN, Hans VAN ANTWERPEN
  • Publication number: 20230197128
    Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.
    Type: Application
    Filed: February 13, 2023
    Publication date: June 22, 2023
    Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
  • Patent number: 11586896
    Abstract: In-memory computing architectures and methods of performing multiply-and-accumulate operations are provided. The method includes sequentially shifting bits of first input bytes into each row in an array of memory cells arranged in rows and columns. Each memory cell is activated based on the bit to produce a bit-line current from each activated memory cell in a column on a shared bit-line proportional to a product of the bit and a weight stored therein. Charges produced by a sum of the bit-line currents in a column are accumulated in first charge-storage banks coupled to a shared bit-line in each of the columns. Concurrently, charges from second input bytes accumulated in second charge-storage banks previously coupled to the columns are sequentially converted into output bytes. The charge-storage banks are exchanged after the first input bytes have been accumulated and the charges from the second input bytes converted. The method then repeats.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: February 21, 2023
    Assignee: INFINEON TECHNOLOGIES LLC
    Inventors: Ramesh Chettuvetty, Vijay Raghavan, Hans Van Antwerpen
  • Patent number: 11581029
    Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: February 14, 2023
    Assignee: LONGITUDE ELASH MEMORY SOLUTIONS LTD
    Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
  • Patent number: 11475632
    Abstract: Disclosed is a method for electro-anatomical mapping. In accordance with the method, surface mesh data is defined to represent the geometry of a myocardial surface. The mesh data comprises mesh points arranged to defined triangles on the myocardial surface and the mesh data is segmented into boundary areas. Point cloud data comprising a plurality of point cloud data points is received and each point cloud data point is assigned to a corresponding mesh point within a boundary area. The point cloud data point and its corresponding mesh point defines a mapping. For each mapping, a difference in a spatial location is determined between the points comprising the mapping. A warping function is selectively applied to spatially relocate the mesh point within each mapping based on the location of the corresponding point cloud data point within the mapping.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: October 18, 2022
    Assignee: NEUCURES INC
    Inventors: Rohit Jain, Kappagantula Gopalakrishna Murty, Vijay Raghavan Dharmapuri Murali, Robert L. Lux
  • Publication number: 20220295124
    Abstract: An embodiment of a digital content distribution system for a delivery of digital materials through digital mailbox systems is described. The digital content distribution system features a virtual processor and a plurality of digital mailbox systems. Each digital mailbox system is configured to operate as a data store addressable by a digital mailbox address that is uniquely associated with a physical address and is assigned to one or more registered users associated with a property identified by the physical address. For instance, a first digital mailbox system is configured to transmit digital materials to and receive digital materials from a second digital mailbox system different than the first digital mailbox system and one or more registered users are provided access to the digital materials received by the first digital mailbox system upon authentication.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 15, 2022
    Inventor: Vijay Raghavan Chetty
  • Patent number: 11231912
    Abstract: An information-technology (IT) blueprint is an executable document that, when executed, can be used to create an IT application such as an e-commerce site. An IT lifecycle blueprint can further be used to manage (e.g., modify) and, ultimately, destroy such an IT application. To this end, an IT lifecycle blueprint can include idempotent methods that achieve the same result whether starting from a blank (real or virtual) infrastructure or from a previously populated infrastructure. In other words, the same method that created an IT application can be used to modify it. A request for a post-deployment modification can be made using a topological representation of a blueprint and highlighting the representations of components to which a selected modification could be applied.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: January 25, 2022
    Assignee: VMware, Inc.
    Inventors: Vijay Raghavan, Yahya Cahyadi, Julie Ann Pickhardt, Kevin Xie, Douglas Cook
  • Publication number: 20210327477
    Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.
    Type: Application
    Filed: April 30, 2021
    Publication date: October 21, 2021
    Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
  • Publication number: 20210271959
    Abstract: In-memory computing architectures and methods of performing multiply-and-accumulate operations are provided. The method includes sequentially shifting bits of first input bytes into each row in an array of memory cells arranged in rows and columns. Each memory cell is activated based on the bit to produce a bit-line current from each activated memory cell in a column on a shared bit-line proportional to a product of the bit and a weight stored therein. Charges produced by a sum of the bit-line currents in a column are accumulated in first charge-storage banks coupled to a shared bit-line in each of the columns. Concurrently, charges from second input bytes accumulated in second charge-storage banks previously coupled to the columns are sequentially converted into output bytes. The charge-storage banks are exchanged after the first input bytes have been accumulated and the charges from the second input bytes converted. The method then repeats.
    Type: Application
    Filed: June 22, 2020
    Publication date: September 2, 2021
    Applicant: Infineon Technologies LLC
    Inventors: Ramesh Chettuvetty, Vijay Raghavan, Hans Van Antwerpen
  • Patent number: 10998019
    Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 4, 2021
    Assignee: Longitude Flash Memory Solutions, Ltd.
    Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
  • Publication number: 20200234746
    Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.
    Type: Application
    Filed: December 16, 2019
    Publication date: July 23, 2020
    Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
  • Patent number: 10664350
    Abstract: An information-technology (IT) blueprint is an executable document that, when executed, can be used to create an IT application such as an e-commerce site. An IT lifecycle blueprint can further be used to manage (e.g., modify) and, ultimately, destroy such an IT application. To this end, an automation engine for the blueprint can include idempotent methods to generate workflows that achieve the same result whether starting from a blank (real or virtual) infrastructure or from a previously populated infrastructure. If a workflow task fails, the workflow that included the task can be re-executed; alternatively, a new workflow can be generated based in part on the application configuration following a fix for the failure.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: May 26, 2020
    Assignee: VMware, Inc.
    Inventors: Vijay Raghavan, Kevin Xie
  • Publication number: 20200066352
    Abstract: A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).
    Type: Application
    Filed: August 5, 2019
    Publication date: February 27, 2020
    Inventors: Bogdan I. Georgescu, Gary P. Mosculak, Vijay Raghavan, Igor G. Kouznetsov
  • Patent number: 10534861
    Abstract: A device may obtain a document. The device may identify a skip value for the document. The skip value may relate to a quantity of words or a quantity of characters that are to be skipped in an n-gram. The device may determine one or more skip n-grams using the skip value for the document. A skip n-gram, of the one or more skip n-grams, may include a sequence of one or more words or one or more characters with a set of occurrences in the document. The sequence of one or more words or one or more characters may include a skip value quantity of words or characters within the sequence. The device may extract one or more terms from the document based on the one or more skip n-grams. The device may provide information identifying the one or more terms.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: January 14, 2020
    Assignee: Accenture Global Services Limited
    Inventors: Anurag Dwarakanath, Aditya Priyadarshi, Bhanu Anand, Bindu Madhav Tummalapalli, Bargav Jayaraman, Nisha Ramachandra, Anitha Chandran, Parvathy Vijay Raghavan, Shalini Chaudhari, Neville Dubash, Sanjay Podder
  • Patent number: 10526273
    Abstract: Disclosed herein are surfactant compounds, that are surface active, liquid, chiral, and micelle forming. Also disclose herein are ionic liquids and compsitions comprising the surfactant compounds.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: January 7, 2020
    Assignee: Vanderbilt University
    Inventors: Prasad L. Polavarapu, Vijay Raghavan
  • Patent number: 10510387
    Abstract: A method for driving a non-volatile memory system is disclosed. A standby detection circuit detects whether the nonvolatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit reduces bias currents provided to drivers of the non-volatile memory system in a standby mode. The non-volatile memory system is operated in the standby mode after the bias currents have been reduced, where an output signal indicating the standby mode is maintained until a read instruction is detected.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: December 17, 2019
    Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
    Inventors: Cristinel Zonte, Vijay Raghavan, Iulian Gradinariu, Gary Peter Moscaluk, Roger Jay Bettman, Vineet Argrawal, Samuel Leshner
  • Patent number: 10373688
    Abstract: A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: August 6, 2019
    Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
    Inventors: Bogdan I. Georgescu, Gary P. Moscaluk, Vijay Raghavan, Igor G. Kouznetsov
  • Publication number: 20190233363
    Abstract: Disclosed herein are surfactant compounds, that are surface active, liquid, chiral, and micelle forming. Also disclose herein are ionic liquids and compsitions comprising the surfactant compounds.
    Type: Application
    Filed: January 24, 2019
    Publication date: August 1, 2019
    Inventors: Prasad L. Polavarapu, Vijay Raghavan