Abstract: A device may obtain a test script document. The device may process the test script document to perform term extraction using one or more term extraction techniques to identify a set of terms of the test script document. The one or more term extraction techniques may include a skip n-gram term extraction technique. One or more terms, of the set of terms, may be located within an n-gram of the test script document. The device may process the test script document to perform hierarchy formation for results of performing term extraction. A relationship between a set of terms, of the set of terms, may be identified using hierarchy formation. The device may generate a functional diagram of the test script document based on the results of performing term extraction and results of performing hierarchy formation. The device may provide information identifying the functional diagram.

Abstract: A device may obtain a document. The device may identify a skip value for the document. The skip value may relate to a quantity of words or a quantity of characters that are to be skipped in an n-gram. The device may determine one or more skip n-grams using the skip value for the document. A skip n-gram, of the one or more skip n-grams, may include a sequence of one or more words or one or more characters with a set of occurrences in the document. The sequence of one or more words or one or more characters may include a skip value quantity of words or characters within the sequence. The device may extract one or more terms from the document based on the one or more skip n-grams. The device may provide information identifying the one or more terms.

Abstract: A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).

Abstract: A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path includes a first inverter and a transistor. The transistor is coupled to the word line. The first path is coupled to receive a first input voltage signal. A second path includes at least the transistor coupled to the word line. At least a portion of the second path is embedded within the first path. The second path is coupled to receive a second input voltage signal.

Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Abstract: A circuit includes a biasing circuit that includes a load circuit coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the load circuit in response to a transition of the ISO signal between a high voltage and a low voltage. The biasing circuit also includes circuitry to generate an isolation delayed (ISO_DEL) signal. The ISO_DEL signal has a high voltage in response to the biasing signal being within a first threshold level and the ISO_DEL signal has a low voltage in response to the biasing signal being within a second threshold level. The biasing circuit outputs the ISO_DEL signal.

Abstract: A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a non-volatile portion and a volatile portion. The non-volatile portion includes a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true, and a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline complement. The volatile portion includes cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage (VPWR) and the first output node, and the second FET coupled between VPWR and the second output node. A gate of the first FET is coupled to the second output node, and a gate of the second FET is coupled to the first output node.

Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.

Abstract: A programming element is provided that defines model attributes in response to mode change events in a graphical modeling environment. Such definition may involve any signal attribute such as dimensions, data types, complexity and sample times. Events that trigger definition of model attributes may be explicit signaling events generated by other elements, elements within the block diagram programming environment, and elements external from the environment. Implicit events may also trigger definition of model attributes, such as a change of attribute in an input signal.

Abstract: According to one embodiment of the invention, a credit redemption system allows a registered user to transmits a request to deposit an amount on a gift card directed to a first retail member and, after verifying that the user has established an account with the credit redemption system, the credit redemption system will deposit the amount on the gift card into the sub-account corresponding to the first retail member. The user may further use the account to make purchases from the first retail member and the amount of the purchase will be deducted from the sub-account corresponding to the first retail member. Furthermore, the user may have a plurality of sub-accounts within the user's account with each sub-account corresponding to a separate retail member.

Abstract: The illustrative embodiments of this invention are directed to a method, a medium and a system for realizing resettable hierarchically scoped variables in a graphical modeling environment on a computing device. The method includes creating at least one resettable variable in a model within the graphical modeling environment, wherein the resettable variable is hierarchically scoped. The resettable variable is reset to a preset value before or during a subsequent invocation of a part of the model that contains the resettable variable. The graphical modeling environment may be a state diagramming environment or the graphical modeling environment may be a time-based graphical modeling environment.

Abstract: Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.

Abstract: Exemplary embodiments provide computer-implemented methods, computer-readable media, and systems for changing the identifier associated with an entity, such as a variable or function, in a portion of code. During editing, a reference may be maintained that identifies the location of each instance of the entity in the code. When the identifier associated with one instance of the entity is changed, the change in the identifier may be propagated throughout the code to change each instance of the identifier in the code. The identifier may be changed without interrupting the workflow of the user and without the need to change to a separate refactoring mode. In some embodiments, a syntactical analysis may be performed and some or all instances of the identifier may be changed based on one or more rules.

Abstract: A method of providing multi-instantiable state templates to a statechart environment is discussed. The method includes the step of providing a graphical definition of an independent state machine object belonging to a statechart. The method further includes the step of instantiating a first instance and a second instance of the independent state machine object in the statechart. The method additionally includes the steps of starting execution of the first instance of the independent state machine object and then stopping execution of the first instance of the state machine object. Additionally, the method includes the step of starting the execution of the second instance of the independent state machine object in the state diagram.

Abstract: A control flow graph may be generated from a model. The control flow graph may be restructured by converting at least one cyclical unstructured region of a control flow graph into a structured region. The restructuring may involve introducing loop head and/or bottom nodes, serving as incident nodes for loop entry or exit, correspondingly. Loop back-edges may be re-routed to loop entry nodes, while all exit nodes may be re-rerouted to loop exit nodes, as long as the control flow within the loop is properly directed using control flow constructs.

Abstract: Exemplary embodiments provide computer-implemented methods, computer-readable media, and systems for changing the identifier associated with an entity, such as a variable or function, in a portion of code. During editing, a reference may be maintained that identifies the location of each instance of the entity in the code. When the identifier associated with one instance of the entity is changed, the change in the identifier may be propagated throughout the code to change each instance of the identifier in the code. The identifier may be changed without interrupting the workflow of the user and without the need to change to a separate refactoring mode. In some embodiments, a syntactical analysis may be performed and some or all instances of the identifier may be changed based on one or more rules.

Abstract: Memory circuits and systems are provided. One memory circuit includes an active memory device, an inactive memory device, and a sense amplifier coupled between the active memory device and the inactive memory device. A reference current is coupled between the inactive memory device and the sense amplifier. The active memory device and the inactive memory device are the same type of memory device and the inactive memory device is a reference device with respect to the active memory device's current. A memory system includes a plurality of the above memory circuit coupled to one another. Methods for sensing current in a memory circuit are also provided. One method includes supplying power to a first memory device and comparing the amount of current in the first memory device and a reference current coupled to a second memory device that is the same type of memory device as the first memory device.

Abstract: A method is provided for interacting with the graphical model is provided. At least one of the plurality of views of the graphical model is parsed to create an intermediate representation. An interactive overlay is displayed using the display device. User interacts with the destination object based on an input instruction via the interactive overlay and modifies the destination object using the input instruction, the modifying allows the destination object to perform a modified operation when the model is executed. The graphical model includes execution semantics and a destination object, where the destination object is influenced by the execution semantics. The graphical model is rendered on a display device based on a selected view.

Abstract: A system, method, distribution system, and computer readable medium for locating an element of a computing environment are described. The invention feature selecting a label within a state diagram associated with a graphical model and processing the selected label to generate a location identifier. The invention also features analyzing the location identifier to determine which element of a graphical model is associated with the location identifier and positioning the graphical model to display the element associated with the location identifier to a user viewing the graphical model.

Abstract: Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.