Abstract: An information-technology (IT) blueprint is an executable document that, when executed, can be used to create an IT application such as an e-commerce site. An IT lifecycle blueprint can further be used to manage (e.g., modify) and, ultimately, destroy such an IT application. To this end, an IT lifecycle blueprint can include idempotent methods that achieve the same result whether starting from a blank (real or virtual) infrastructure or from a previously populated infrastructure. To effect a modification that is not within the scope of the blueprint that created the IT application, a new lifecycle blueprint can be created, if necessary, and executed to effect the modification. In a sense, the new lifecycle blueprint replaces the old lifecycle blueprint as a manager tool for the IT application.

Abstract: A device may obtain a document. The device may identify a skip value for the document. The skip value may relate to a quantity of words or a quantity of characters that are to be skipped in an n-gram. The device may determine one or more skip n-grams using the skip value for the document. A skip n-gram, of the one or more skip n-grams, may include a sequence of one or more words or one or more characters with a set of occurrences in the document. The sequence of one or more words or one or more characters may include a skip value quantity of words or characters within the sequence. The device may extract one or more terms from the document based on the one or more skip n-grams. The device may provide information identifying the one or more terms.

Abstract: A method for driving a non-volatile memory system is disclosed. A standby detection circuit detects whether the nonvolatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit reduces bias currents provided to drivers of the non-volatile memory system in a standby mode. The non-volatile memory system is operated in the standby mode after the bias currents have been reduced, where an output signal indicating the standby mode is maintained until a read instruction is detected.

Abstract: A device may obtain a test script document. The device may process the test script document to perform term extraction using one or more term extraction techniques to identify a set of terms of the test script document. The one or more term extraction techniques may include a skip n-gram term extraction technique. One or more terms, of the set of terms, may be located within an n-gram of the test script document. The device may process the test script document to perform hierarchy formation for results of performing term extraction. A relationship between a set of terms, of the set of terms, may be identified using hierarchy formation. The device may generate a functional diagram of the test script document based on the results of performing term extraction and results of performing hierarchy formation. The device may provide information identifying the functional diagram.

Abstract: A device may obtain a document. The device may identify a skip value for the document. The skip value may relate to a quantity of words or a quantity of characters that are to be skipped in an n-gram. The device may determine one or more skip n-grams using the skip value for the document. A skip n-gram, of the one or more skip n-grams, may include a sequence of one or more words or one or more characters with a set of occurrences in the document. The sequence of one or more words or one or more characters may include a skip value quantity of words or characters within the sequence. The device may extract one or more terms from the document based on the one or more skip n-grams. The device may provide information identifying the one or more terms.

Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.

Abstract: An information-technology (IT) blueprint is an executable document that, when executed, can be used to create an IT application such as an e-commerce site. An IT lifecycle blueprint can further be used to manage (e.g., modify) and, ultimately, destroy such an IT application. To this end, an automation engine for the blueprint can include idempotent methods to generate workflows that achieve the same result whether starting from a blank (real or virtual) infrastructure or from a previously populated infrastructure. If a workflow task fails, the workflow that included the task can be re-executed; alternatively, a new workflow can be generated based in part on the application configuration following a fix for the failure.

Abstract: An information-technology (IT) blueprint is an executable document that, when executed, can be used to create an IT application such as an e-commerce site. An IT lifecycle blueprint can further be used to manage (e.g., modify) and, ultimately, destroy such an IT application. To this end, an IT lifecycle blueprint can include idempotent methods that achieve the same result whether starting from a blank (real or virtual) infrastructure or from a previously populated infrastructure. To effect a modification that is not within the scope of the blueprint that created the IT application, a new lifecycle blueprint can be created, if necessary, and executed to effect the modification. In a sense, the new lifecycle blueprint replaces the old lifecycle blueprint as a manager tool for the IT application.

Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.

Abstract: An information-technology (IT) blueprint is an executable document that, when executed, can be used to create an IT application such as an e-commerce site. An IT lifecycle blueprint can further be used to manage (e.g., modify) and, ultimately, destroy such an IT application. To this end, an IT lifecycle blueprint can include idempotent methods that achieve the same result whether starting from a blank (real or virtual) infrastructure or from a previously populated infrastructure. In other words, the same method that created an IT application can be used to modify it. A request for a post-deployment modification can be made using a topological representation of a blueprint and highlighting the representations of components to which a selected modification could be applied.

Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage node of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.

Abstract: A circuit includes a biasing circuit that includes a diode stack coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a transistor, a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the diode stack in response to a transition of the ISO signal between a first voltage and a second voltage. The biasing circuit also is configured to output a signal to a level shifter to hold an output of the level shifter in a known state for a specified amount of time after power-up of the circuit for proper operation of the level shifter.

Abstract: Exemplary embodiments provide techniques for replacing a portion of a state diagram with a generalized, canonical version of the portion. The canonicalized version mimics the structure or semantics (or both) of the portion of the state diagram, although the canonicalized version need not be a perfect match for the structure or semantics of the portion. Exemplary embodiments further provide techniques for identifying a portion of a state diagram for reuse, and generating a canonicalized version of the portion.

Abstract: A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).

Abstract: A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).

Abstract: A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a non-volatile portion and a volatile portion. The non-volatile portion includes a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true, and a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline complement. The volatile portion includes cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage (VPWR) and the first output node, and the second FET coupled between VPWR and the second output node. A gate of the first FET is coupled to the second output node, and a gate of the second FET is coupled to the first output node.

Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Abstract: A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path includes a first inverter and a transistor. The transistor is coupled to the word line. The first path is coupled to receive a first input voltage signal. A second path includes at least the transistor coupled to the word line. At least a portion of the second path is embedded within the first path. The second path is coupled to receive a second input voltage signal.

Abstract: Exemplary embodiments provide computer-implemented methods, computer-readable media, and systems for changing the identifier associated with an entity, such as a variable or function, in a portion of code. During editing, a reference may be maintained that identifies the location of each instance of the entity in the code. When the identifier associated with one instance of the entity is changed, the change in the identifier may be propagated throughout the code to change each instance of the identifier in the code. The identifier may be changed without interrupting the workflow of the user and without the need to change to a separate refactoring mode. In some embodiments, a syntactical analysis may be performed and some or all instances of the identifier may be changed based on one or more rules.