Patents by Inventor Vikram Joshi

Vikram Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6441414
    Abstract: A ferroelectric non-volatile memory in which each memory cell consists of a single electronic element, a ferroelectric FET. The FET includes a source, drain, gate and substrate. The fact that the drain to source current, lds, is always negative if a substrate to drain bias, Vss, of 0.8 volts or more is applied, permits the creation of a read and write truth table. A gate voltage equal to one truth table logic value is applied via a column decoder and a substrate bias equal to another truth table logic value is applied via a row decoder to write to the memory a resultant lds logic state, which can be read whenever a voltage is placed across the source and drain.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: August 27, 2002
    Assignee: Symetrix Corporation
    Inventors: Myoungho Lim, Vikram Joshi, Jeffrey W. Bacon, Joseph D. Cuchiaro, Larry D. McMillan, Carlos A. Paz de Araujo
  • Patent number: 6437380
    Abstract: An integrated circuit device includes a thin film of bismuth-containing layered superlattice material having a thickness not exceeding 100 nm, a capping layer thin film of bismuth tantalate, and an electrode. The capping layer has a thickness in a range of from 3 nm to 30 nm and is deposited between the thin film of layered superlattice material and the electrode to increase dielectric breakdown voltage. Preferably the capping layer contains an excess amount of bismuth relative to the stoichiometrically balanced amount represented by the balanced stoichiometric formula BiTaO4. Preferably, the layered superlattice material is ferroelectric SBT or SBTN. Preferably, the integrated circuit device is a nonvolatile ferroelectric memory. Heating treatments for fabrication of the integrated circuit device containing the bismuth tantalate capping layerare conducted at temperatures not exceeding 700° C., preferably in a range of from 650° C. to 700° C.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: August 20, 2002
    Assignee: Symetrix Corporation
    Inventors: Myoungho Lim, Vikram Joshi, Narayan Solayappan, Larry D. McMillan, Carlos A. Paz de Araujo
  • Patent number: 6373743
    Abstract: A ferroelectric non-volatile memory comprising: a plurality of memory cells each containing a ferroelectric FET, each of said ferroelectric FETs having a source, a drain, a substrate, and a gate. The FETs are arranged in an array comprising a plurality of rows and a plurality of columns. There are a plurality of row select lines, each associated with one of the rows of said ferroelectric FETs, and a plurality of column select lines, each associated with one of the columns of ferroelectric FETs. Each of the sources is directly electrically connected to its associated row select line, and each of the drains is directly electrically connected to its associated column select line. The source and substrate of each FET are also directly electrically connected. A memory cell is read by connecting its row select line to ground, and its column select line to a small voltage. All the gates, and the row select lines of non-selected cells are open or connected to a high resistance source.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: April 16, 2002
    Assignee: Symetrix Corporation
    Inventors: Zheng Chen, Myoungho Lim, Vikram Joshi, Carlos A. Paz de Araujo, Larry D. McMillan
  • Patent number: 6370056
    Abstract: A ferroelectric non-volatile memory comprising: a plurality of memory cells, each containing an FeFET and a MOSFET, each of said FeFETs having a source, a drain, a substrate, and a gate, and each MOSFET having a pair of source/drains and a gate. The cells are arranged in an array comprising a plurality of rows and a plurality of columns. A gate line and a bit line are associated with each column, and a word line, a drain line, and a substrate line are associated with each row. One source/drain of each MOSFET is connected to its corresponding gate line; the other source/drain is connected to the gate of the FeFET in the cell. The gate of the MOSFET is connected to its corresponding word line which provides a write and erase enable signal. The drain of the FeFET is connected to its corresponding drain line, and the source of the FeFET is connected to its corresponding bit line. The substrate of each FeFET is connected to its corresponding substrate line.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: April 9, 2002
    Assignee: Symetrix Corporation
    Inventors: Zheng Chen, Vikram Joshi, Myoungho Lim, Carlos A. Paz de Araujo, Larry D. McMillan
  • Patent number: 6339238
    Abstract: A ferroelectric non-volatile memory in which each memory cell consists of a single electronic element, a ferroelectric FET. The FET includes a source, drain, gate and substrate. A cell is selected for writing or reading by application of bias voltages to the source, drain, gate or substrate. A gate voltage equal to one truth table logic value and a drain voltage equal to another truth table logic value are applied via a row decoder, and a substrate bias equal to a third truth table logic value is applied via a column decoder to write to the memory a resultant Ids logic state, which can be non-destructively read by placing a voltage across the source and drain.
    Type: Grant
    Filed: June 10, 1999
    Date of Patent: January 15, 2002
    Assignee: Symetrix Corporation
    Inventors: Myoungho Lim, Vikram Joshi, Joseph D. Cuchiaro, Larry D. McMillan, Carlos A. Paz de Araujo
  • Patent number: 6322849
    Abstract: An integrated circuit is formed containing a metal-oxide ferroelectric thin film. An inert-gas recovery anneal is conducted to reverse the degradation of ferroelectric properties caused by hydrogen. The inert-gas recovery anneal is conducted in an unreactive gas atmosphere at a temperature range from 300° to 1000° C. for a time period from one minute to two hours. Preferably, the metal-oxide thin film comprises layered superlattice material. Preferably, the layered superlattice material comprises strontium bismuth tantalate or strontium bismuth tantalum niobate. If the integrated circuit manufacture includes a forming-gas anneal, then the inert-gas recovery anneal is performed after the forming-gas anneal, preferably at or near the same temperature and for the same time duration as the forming-gas anneal.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: November 27, 2001
    Assignees: Symetrix Corporation, Spemens AG
    Inventors: Vikram Joshi, Narayan Solayappan, Walter Hartner, Günther Schindler
  • Publication number: 20010013614
    Abstract: A diffusion barrier layer in an integrated circuit is located to inhibit undesired diffusion of chemical species from local interconnects into layered superlattice material in a thin film memory capacitor. The diffusion barrier layer comprises iridium oxide. The thin film of layered superlattice material is ferroelectric or nonferroelectric, high-dielectric constant material. Preferably, the thin film comprises ferroelectric layered superlattice material. The diffusion barrier layer is located between a local interconnect and the memory capacitor. Preferably, the diffusion barrier layer is in direct contact with the local interconnect. The iridium-oxide diffusion barrier is effective for preventing diffusion of metals, silicon and other chemical species.
    Type: Application
    Filed: January 24, 2001
    Publication date: August 16, 2001
    Inventors: Vikram Joshi, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
  • Publication number: 20010012698
    Abstract: A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of Bi2O3 with an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulas AB2O6, A2B2O7 and A2Bi2B2O10, wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (BaxSr1−x)(TayNb1−y)2O6, where 0≦x≦1.0 and 0≦y≦1.0; (BaxSr1−x)2(TayNb1−y)2O7, where 0≦x≦1.0 and 0≦y≦1.0; and (BaxSr1−x)2Bi2(TayNby−1)2O10, where 0≦x≦1.0 and 0≦y≦1.0. Thin films according to the invention have a relative dielectric constant ≧40, and preferably about 100.
    Type: Application
    Filed: March 2, 2001
    Publication date: August 9, 2001
    Applicant: Symetrix Corporation
    Inventors: Shinichiro Hayashi, Vikram Joshi, Narayan Solayappan, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
  • Patent number: 6245580
    Abstract: A coating of liquid precursor containing a metal is applied to a first electrode, baked on a hot plate in oxygen ambient at a temperature not exceeding 300° C. for five minutes, then RTP annealed at 675° C. for 30 seconds. The coating is then annealed in oxygen or nitrogen ambient at 700° C. for one hour to form a thin film of layered superlattice material with a thickness not exceeding 100 nm. A second electrode is applied to form a capacitor, and a second anneal is performed in oxygen or nitrogen ambient at a temperature not exceeding 700° C. If the material is strontium bismuth tantalate, the precursor contains u mole-equivalents of strontium, v mole-equivalents of bismuth, and w mole-equivalents of tantalum, where 0.8≦u≦1.0, 2.0≦v≦2.3, and 1.9≦w≦2.1.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: June 12, 2001
    Assignee: Symetrix Corporation
    Inventors: Narayan Solayappan, Vikram Joshi, Carlos A. Paz de Araujo
  • Publication number: 20010002273
    Abstract: An integrated circuit is formed containing a metal-oxide ferroelectric thin film. An inert-gas recovery anneal is conducted to reverse the degradation of ferroelectric properties caused by hydrogen. The inert-gas recovery anneal is conducted in an unreactive gas atmosphere at a temperature range from 300° to 1000° C. for a time period from one minute to two hours. Preferably, the metal-oxide thin film comprises layered superlattice material. Preferably, the layered superlattice material comprises strontium bismuth tantalate or strontium bismuth tantalum niobate. If the integrated circuit manufacture includes a forming-gas anneal, then the inert-gas recovery anneal is performed after the forming-gas anneal, preferably at or near the same temperature and for the same time duration as the forming-gas anneal.
    Type: Application
    Filed: November 13, 1998
    Publication date: May 31, 2001
    Inventors: VIKRAM JOSHI, NARAYAN SOLAYAPPAN, WALTER HARTNER, GUNTHER SCHINDLER
  • Patent number: 6171934
    Abstract: An integrated circuit is formed containing a metal-oxide ferroelectric thin film. An voltage-cycling recovery process is conducted to reverse the degradation of ferroelectric properties caused by hydrogen. The voltage-cycling recovery process is conducted by applying from 104 to 1011 voltage cycles with a voltage amplitude of from 1 to 15 volts. Conducting voltage-cycling at a higher temperature in the range 30-200° C. enhances recovery. Preferably the metal oxide thin film comprises layered superlattice material. Preferably the layered superlattice material comprises strontium bismuth tantalate or strontium bismuth tantalum niobate. If the integrated circuit manufacture includes a forming-gas anneal, then the voltage-cycling recovery process is performed after the forming-gas anneal.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: January 9, 2001
    Assignees: Symetrix Corporation, Siemens Aktiengesellschaft
    Inventors: Vikram Joshi, Narayan Solayappan, Walter Hartner, G{umlaut over (u)}nther Schindler
  • Patent number: 6104049
    Abstract: A coating of liquid precursor containing a metal is applied to a first electrode, baked on a hot plate in oxygen ambient at a temperature not exceeding 300.degree. C. for five minutes, then RTP annealed at 675.degree. C. for 30 seconds. The coating is then annealed in oxygen or nitrogen ambient at 700.degree. C. for one hour to form a thin film of layered superlattice material with a thickness not exceeding 90 nm. A second electrode is applied to form a capacitor, and a post-anneal is performed in oxygen or nitrogen ambient at a temperature not exceeding 700.degree. C. If the material is strontium bismuth tantalate, the precursor contains u mole-equivalents of strontium, v mole-equivalents of bismuth, and w mole-equivalents of tantalum, where 0.8.ltoreq.u.ltoreq.1.0, 2.0.ltoreq.v.ltoreq.2.3, and 1.9.ltoreq.w.ltoreq.2.1.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: August 15, 2000
    Assignee: Symetrix Corporation
    Inventors: Narayan Solayappan, Vikram Joshi, Carlos A. Paz de Araujo, Larry D. McMillan, Shinichiro Hayashi, Tatsuo Otsuki
  • Patent number: 6037046
    Abstract: An electromagnetic wave absorption panel for use in building construction includes a protective tile layer, an absorber layer, a metal reflective layer, and a building support layer, such as concrete. The absorber layer is multi-component structure, such as: a high dielectric constant layer and ferrite layer; a ferrite layer and a low dielectric constant layer; a ferrite and a polymer; a polymer and a material having a higher dielectric constant than the polymer; a ferroelectric, a ferrite, and a polymer; a ferrite, a polymer, and a high dielectric constant material; and a high dielectric constant material, a material in which the imaginary part of the permeability is greater than or equal to the real part of the permeability, and a low dielectric constant material. The invention also includes combinations of the above, such as: a high dielectric constant material, a ferrite, and a low dielectric constant material; and multiple layers of a ferrite and a polymer.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: March 14, 2000
    Assignees: Symetrix Corporation, Fujita Corporation
    Inventors: Vikram Joshi, Kenichi Kimura, Carlos A. Paz de Araujo, Hiroshi Kiyokawa
  • Patent number: 5962069
    Abstract: A liquid precursor containing a metal is applied to a first electrode, dried in air at a first temperature of 160.degree. C. and then a second temperature of 260.degree. C., RTP baked at a temperature of 300.degree. C. in oxygen, RTP baked at a temperature of 650.degree. C. in nitrogen, and annealed at a temperature of 800.degree. C. in nitrogen to form a strontium bismuth tantalate layered superlattice material. A second electrode is deposited and then the device is patterned to form a capacitor, and a second anneal is performed at a temperature of 800.degree. C. in nitrogen. Alternatively, the second anneal may be performed in oxygen at a temperature of 600.degree. C. or less. In this manner, a high electronic quality thin film of a layered superlattice material is fabricated without a high-temperature oxygen anneal.
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: October 5, 1999
    Assignees: Symetrix Corporation, Siemens Aktiengesellschaft
    Inventors: Gunther Schindler, Walter Hartner, Carlos Mazure, Narayan Solayappan, Vikram Joshi, Gary F. Derbenwick
  • Patent number: 5888585
    Abstract: A charge storage device, such as an integrated circuit memory, including a dielectric comprising a barium-strontium-niobium oxide. A liquid precursor including the metals barium, strontium, and niobium is prepared and applied to a platinum electrode. The precursor is baked and annealed to form a dielectric having the formula Ba.sub.x Sr.sub.y Nb.sub.z O.sub.30, where x=1.3 to 3.5, y=1.5 to 3.7, and z =10. A top platinum electrode is then formed to provide a memory cell capacitor. Optimum results to date have been obtained with Ba.sub.2 Sr.sub.3 Nb.sub.10 O.sub.30, which yields a memory cell dielectric with dielectric constant over 1000 and a leakage current of less than 10.sup.-5 amperes per square centimeter for voltages up to 5 volts.
    Type: Grant
    Filed: December 16, 1996
    Date of Patent: March 30, 1999
    Assignee: Symetrix Corporation
    Inventors: Joseph D. Cuchiaro, Vikram Joshi, Claudia P. DaCruz, John M. McNelis, Carlos A. Paz de Araujo
  • Patent number: 5853889
    Abstract: An electromagnetic wave absorption panel for use in building construction includes a protective tile layer, an absorber layer, a metal reflective layer, and a building support layer, such as concrete. The absorber layer utilizes novel materials including high dielectric constant materials, such as ABO.sub.3 type perovskites, layered superlattice materials, conducting oxides, and signet magnetics, ferroelectrics, such as ABO.sub.3 type perovskites and layered superlattice materials, garnets, a nickel-zinc ferrite, Ni.sub.0.4 Zn.sub.0.6 Fe.sub.2 O.sub.4, and polymer-ceramic composites of the above materials.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: December 29, 1998
    Assignees: Symetrix Corporation, Fujita Corporation
    Inventors: Vikram Joshi, Kenichi Kimura, Carlos A. Paz de Araujo, Hiroshi Kiyokawa
  • Patent number: 5853500
    Abstract: A liquid precursor containing barium, strontium, and titanium, is applied to a first electrode, dried in air at a first temperature of 160.degree. C. and then a second temperature of 400.degree. C., and annealed at a temperature of 800.degree. C. in nitrogen to form a thin film of barium strontium titanate. A second electrode is deposited and then the device is patterned to form a capacitor, and a second anneal is performed at a temperature of 800.degree. C. in nitrogen. In this manner, a high electronic quality thin film of barium strontium titanate is fabricated without a high-temperature oxygen anneal.
    Type: Grant
    Filed: July 18, 1997
    Date of Patent: December 29, 1998
    Assignee: Symetrix Corporation
    Inventors: Vikram Joshi, Carlos A. Paz de Araujo
  • Patent number: 5811847
    Abstract: An integrated circuit memory, MMIC, or other device including a dielectric comprising lead-tin zirconium-titanium oxide (PSZT). The proportion of tin ranges from 30% to 50% of the total amount of tin, zirconium and titanium. The dielectric is formed by applying a first liquid precursor having 10% excess lead to a substrate and heating it to form a first PSZT thin film, applying a second liquid precursor having 5% excess lead to the first thin film and heating to form a second thin film, then applying the first liquid precursor and heating to form a third thin film, and annealing the three thin films together to form a PSZT dielectric layer.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: September 22, 1998
    Assignee: Symetrix Corporation
    Inventors: Vikram Joshi, Joseph D. Cuchiaro, Carlos A. Paz de Araujo, Larry D. McMillan
  • Patent number: 5751034
    Abstract: A charge storage device, such as an integrated circuit memory, including a dielectric comprising a barium-strontium-niobium oxide. A liquid precursor including the metals barium, strontium, and niobium is prepared and applied to a platinum electrode. The precursor is baked and annealed to form a dielectric having the formula Ba.sub.x Sr.sub.y Nb.sub.z O.sub.30, where x=1.3 to 3.5, y=1.5 to 3.7, and z=10. A top platinum electrode is then formed to provide a memory cell capacitor. Optimum results to date have been obtained with Ba.sub.2 Sr.sub.3 Nb.sub.10 O.sub.30, which yields a memory cell dielectric with dielectric constant over 1000 and a leakage current of less than 10.sup.-5 amperes per square centimeter for voltages up to 5 volts.
    Type: Grant
    Filed: June 12, 1997
    Date of Patent: May 12, 1998
    Assignee: Symetrix Corporation
    Inventors: Joseph D. Cuchiaro, Vikram Joshi, Claudia P. DaCruz, John M. McNelis, Carlos A. Paz de Araujo