Abstract: A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode. An isolation break includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench. The first insulator layer and the second insulator layer(s) are between the first RDL electrode and the second RDL electrode. The isolation may separate, for example, voltage domains having different voltage levels. A related method is also disclosed. The isolation may also include a vertical portion using the first RDL electrode and another electrode in a metal layer separated from the first RDL electrode by a plurality of interconnect dielectric layers.

Abstract: A structure includes a first air gap including a first opening defined in a first dielectric layer and a second dielectric layer over the first opening and closing an end portion of the first opening. A second air gap may be over at least a portion of the first air gap. The second air gap includes a second opening defined in the second dielectric layer and a third dielectric layer over the second opening and closing an end portion of the second opening. The second air gap has a pointed lower end portion. In another version, the structure includes a first air gap in a first dielectric layer, a second dielectric layer over the first air gap, and a discrete dielectric member positioned in the second dielectric layer and aligned over the first air gap.

Abstract: The disclosed subject matter relates generally to structures in semiconductor devices and integrated circuit (IC) chips. More particularly, the present disclosure relates to a metal-dielectric-metal capacitor having electrically inactive metal layers arranged in an interconnect level that is below another interconnect level containing two sets of metal lines interdigitated with each other.

Abstract: Structures that include a layer stack for a resistive memory element and methods of forming a structure that includes a layer stack for a resistive memory element. The structure comprises a resistive memory element including a first electrode, a second electrode, and a switching layer disposed between the second electrode and the first electrode. The first electrode includes a first layer and a second layer between the first layer and the switching layer. The switching layer has a first thickness, and the second layer of the first electrode has a second thickness that is less than the first thickness of the switching layer.

Abstract: A thin-film resistor (TFR) includes conductive line(s) and a resistive layer over the conductive line(s). The TFR also includes at least one viabar structure coupled to the resistive layer and including a first viabar portion electrically connected to the resistive layer at an edge thereof and a second viabar portion electrically connected to the conductive line(s). In other cases, a viabar structures partially land over the resistive layer and are electrically connected to an edge of the resistive layer and partially land on the conductive line(s). Among other advantages, the viabar structure reduces current crowding from tight contact spacing, and allows alternative routing of interconnects to the TFR.

Abstract: Semiconductor devices including seal rings and method of making the same is provided. A semiconductor device comprises an interconnect layer over a substrate. The interconnect layer comprises a barrier layer over a dielectric layer. A seal ring is in the interconnect layer and the seal ring extends through the interconnect layer to abut the substrate. An insulator layer is around the seal ring and the insulator layer spaces the seal ring from the barrier layer. A protective structure is laterally adjacent to the seal ring and the protective structure extends through the interconnect structure to abut the substrate. The seal ring may be segmented and comprises a first segment in a first trench in an interconnect stack, and a second segment in a second trench in the interconnect stack.

Abstract: A thin-film resistor (TFR) includes conductive line(s) and a resistive layer over the conductive line(s). The TFR also includes at least one viabar structure coupled to the resistive layer and including a first viabar portion electrically connected to the resistive layer at an edge thereof and a second viabar portion electrically connected to the conductive line(s). In other cases, a viabar structures partially land over the resistive layer and are electrically connected to an edge of the resistive layer and partially land on the conductive line(s). Among other advantages, the viabar structure reduces current crowding from tight contact spacing, and allows alternative routing of interconnects to the TFR.

Abstract: A bonded semiconductor device includes a first semiconductor device, a second semiconductor device face bonded to the first semiconductor device, at least one metal plug in a middle of line layer of the first semiconductor device, and a through oxide via (TOV) coupled to the at least one metal plug and a metal line in a backside region of the first semiconductor device.

Abstract: Methods of forming semiconductor devices including an air gap extending through at least one metal layer, and the semiconductor device so formed, are disclosed. The air gap has a lower portion that contacts a silicide layer over a gate body of a transistor gate and has an inverted T-shape over the gate body. The air gap reduces the capacitance between a transistor gate in a device layer and adjacent wires and vias used to contact the source and drain of the transistor.

Abstract: A structure includes an integrated circuit (IC) chip including an IC region and a peripheral region around the IC region. A first continuous deep trench (DT) is defined in the peripheral region around the IC region, and an air gap is defined by a first dielectric liner in the first continuous DT. The structure provides a moisture barrier and a crack stop.

Abstract: The embodiments herein relate to semiconductor devices having a non-uniform pattern density for hybrid bonding. A semiconductor structure is provided. The semiconductor structure may include a semiconductor device having a substrate, a device region over the substrate, a bonding region over the device region, and a plurality of bonding structures in the bonding region. The bonding region may include a first bonding area having a first pattern density, a second bonding area having a second pattern density adjacent to the first bonding area, and a third bonding area having a third pattern density adjacent to the second bonding area. The plurality of bonding structures in the bonding region may include a first bonding structure in the first bonding area, a second bonding structure in the second bonding area, and a third bonding structure in the third bonding area.

Abstract: A structure includes an IC die having an edge perimeter and an indentation extending inwardly at a portion of the edge perimeter. The structure also includes a scribe region including a first section defined along the edge perimeter of the IC die and a second section defined in the indentation. The first section has a first width relative to the edge perimeter and the second section has a second width relative to the edge perimeter greater than the first width. The second section of the scribe region provides a wider, enlarged area for wider in-frame structures, such as alignment marks, while the first section of the scribe region has a smaller width to provide area for smaller in-frame structures.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to via bars interleaved between conductive plates of a capacitor structure and methods of manufacture. The structure includes: a capacitor structure having a plurality of capacitor plates within layers of dielectric material; a wiring structure in a lower layer of the dielectric material, the wiring structure electrically connecting to one of the capacitor plates; and a plurality of via bars within the layers of dielectric material and interleaved with the plurality of capacitor plates. The plurality of via bars have a different width dimension than the plurality of capacitor plates.

Abstract: The embodiments herein relate to structures of MIM capacitors including a sealed void and methods of forming the same. According to an aspect of the present disclosure, a structure is provided. The structure includes a MIM capacitor having a first electrode and a second electrode over the first electrode. A conductive via is laterally adjacent to the second electrode and electrically connected to the first electrode. A void extends around an outer perimeter of the second electrode.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to capacitor structures and methods of manufacture. The structure includes: an airgap provided within a dielectric material; an insulator material across a top of the airgap and on a surface of the dielectric material; and a capacitor provided within the dielectric material and lined with the insulator material.

Abstract: Structures including a photodetector, such as a single-photon avalanche diode, and related methods. The structure comprises a semiconductor layer, a photodetector including a well in the semiconductor layer, and a deep trench isolation region including a first conductor layer extending through the semiconductor layer. The deep trench isolation region surrounds the photodetector. The structure further comprises a bond pad, and an electrical connection including a second conductor layer extending from the bond pad through the semiconductor layer.

Abstract: The disclosed subject matter relates generally to capacitors in semiconductor devices and integrated circuit (IC) chips. More particularly, the present disclosure relates to a metal-dielectric-metal capacitor having electrically floating metal layers and an interconnect level that is devoid of any metal layers. The present disclosure provides a capacitor having a first interconnect level above a substrate, a first plurality of metal layers in the first interconnect level, a second interconnect level above the first interconnect level, a second plurality of metal layers in the second interconnect level, in which the metal layers in the second plurality of metal layers are electrically floating, a third interconnect level above the second interconnect level, the third interconnect level is devoid of any metal layers, a fourth interconnect level above the third interconnect level, and a third plurality of metal layers in the fourth interconnect level.

Abstract: Structures that include a layer stack for a resistive memory element and methods of forming a structure that includes a layer stack for a resistive memory element. The structure comprises a resistive memory element including a first electrode, a second electrode, and a switching layer disposed between the second electrode and the first electrode. The first electrode includes a first layer and a second layer between the first layer and the switching layer. The switching layer has a first thickness, and the second layer of the first electrode has a second thickness that is less than the first thickness of the switching layer.

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure includes a first field-effect transistor on a first substrate and a second field-effect transistor on a second substrate. The first field-effect transistor includes a first gate, and the second field-effect transistor includes a second gate. The structure further includes a first interconnect structure on the first substrate and a second interconnect structure on the second substrate. The first interconnect structure includes a first metal feature connected to the first gate, and the first metal feature has a first surface. The second interconnect structure includes a second metal feature connected to the second gate, and the second metal feature has a second surface that is connected to the first surface of the first metal feature.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure including a switching element arranged between a pair of conductors, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure includes a switching element arranged between a pair of conductors, in which the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.