Patents by Inventor Wanbing YI

Wanbing YI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10720580
    Abstract: A device including a reduced top RRAM electrode structure, and method of production thereof. Embodiments include a bottom resistive random-access memory (RRAM) electrode structure over a plurality of lower metal level contacts formed laterally separated in a substrate; a resistive switching structure over the bottom RRAM electrode structure; a top RRAM electrode structure over the resistive switching structure; a protective structure over the top RRAM electrode structure; an encapsulation structure over the bottom RRAM electrode structure and on sidewalls of the resistive switching structure, the top RRAM electrode structure and the protective structure; and an Nblock layer over the substrate.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 21, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Curtis Chun-I Hsieh, Wei-Hui Hsu, Wanbing Yi, Yi Jiang, Juan Boon Tan
  • Patent number: 10707358
    Abstract: A semiconductor device having a substrate with at least one photo-detecting region and at least one bond pad is provided. A first passivation layer is deposited over the substrate and over step portions at the edges of the bond pad and a trench having sidewalls and a bottom surface is formed in the substrate. A light shielding layer is deposited over the first passivation layer and covering the trench sidewalls. The light shielding layer has end portions at the photo-detecting region, at step portions at the edges of the bond pad and at the bottom surface of the trench. A second passivation layer is deposited over the light shielding layer. A third passivation layer is deposited over the end portions of the light shielding layer at the photo-detecting region and at the step portions at edges of the bond pad.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Juan Boon Tan, Kiok Boone Elgin Quek, Khee Yong Lim, Chim Seng Seet, Rajesh Nair
  • Patent number: 10693054
    Abstract: A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Wanbing Yi, Curtis Chun-I Hsieh, Yi Jiang, Juan Boon Tan, Benfu Lin
  • Publication number: 20200194496
    Abstract: Integrated circuits with embedded memory structures, and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming from a first metallization layer a first lower conductive interconnect in a first region of a dielectric layer and a second lower conductive interconnect in a second region of the dielectric layer. The method includes forming a memory structure in the first region. Further, the method includes depositing an interlayer dielectric over the first region and over the second region. Also, the method includes forming from a second metallization layer a first upper conductive interconnect over the interlayer dielectric, wherein the first upper conductive interconnect is coupled to the memory structure.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Inventors: Curtis Chun-I Hsieh, Wanbing Yi, Yi Jiang, Juan Boon Tan
  • Patent number: 10651380
    Abstract: In a non-limiting embodiment, a device may be formed having a substrate that has at least a first region. A base dielectric layer is arranged over the substrate. The base dielectric layer includes an interconnect in the first region. A first electrode is arranged over the interconnect in the first region. A mask structure is arranged over the first electrode. At least one spacer stack is arranged at least partially around the mask structure and the first electrode. The spacer stack(s) includes a resistive switching element at least partially lining sidewalls of the mask structure and the first electrode, and a second electrode arranged over the resistive switching element.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Curtis Chun-I Hsieh, Wei-Hui Hsu, Wanbing Yi, Yi Jiang, Juan Boon Tan
  • Publication number: 20200127197
    Abstract: A device including a reduced top RRAM electrode structure, and method of production thereof. Embodiments include a bottom resistive random-access memory (RRAM) electrode structure over a plurality of lower metal level contact formed laterally separated in a substrate; a resistive switching structure over the bottom RRAM electrode structure; a top RRAM electrode structure over the resistive switching structure; a protective structure over the top RRAM electrode structure; an encapsulation structure over the bottom RRAM electrode structure and on sidewalls of the resistive switching structure, the top RRAM electrode structure and the protective structure; and an Nblock layer over the substrate.
    Type: Application
    Filed: October 22, 2018
    Publication date: April 23, 2020
    Inventors: Curtis Chun-I HSIEH, Wei-Hui HSU, Wanbing YI, Yi JIANG, Juan Boon TAN
  • Patent number: 10608046
    Abstract: Devices and methods of forming a device. A two-terminal device element includes a device stack coupled between first and second terminals. The first terminal contacts a metal line in an underlying interconnect level, and the second terminal is formed over the device layer. An encapsulation liner covers exposed side surfaces of the device stack of the two-terminal device element. A dual damascene interconnect is coupled to the two-terminal device element.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: March 31, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Juan Boon Tan, Soh Yun Siah, Hai Cong, Alex See, Young Seon You, Danny Pak-Chum Shum, Hyunwoo Yang
  • Publication number: 20200091020
    Abstract: A semiconductor interconnect structure including a conductive layer, a plurality of interconnect vias and a pad is presented. The interconnect vias are formed over the conductive layer and the pad having a substantially flat surface is formed over the plurality of interconnect vias. The conductive layer may be a conductive line and/or a conductive plate connected to a conductive line.
    Type: Application
    Filed: September 13, 2018
    Publication date: March 19, 2020
    Inventors: WANBING YI, LAIQIANG LUO, XINGYU CHEN, FAN ZHANG, JUAN BOON TAN
  • Patent number: 10593728
    Abstract: Integrated circuits and methods for fabricating magnetic tunnel junction (MTJ) structures and integrated circuits are provided. An exemplary method for fabricating an integrated circuit including a magnetic tunnel junction (MTJ) structure includes forming magnetic tunnel junction (MTJ) layers over a substrate. Further, the method includes forming a conductive pillar over the MTJ layers, wherein the conductive pillar is formed with an uppermost surface, and wherein the uppermost surface is not planarized. Also, the method includes etching the MTJ layers to form a pillar structure from portions of the MTJ layers underlying the conductive pillar.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 17, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Curtis Chun-I Hsieh, Wanbing Yi, Yi Jiang, Juan Boon Tan
  • Patent number: 10580968
    Abstract: In a non-limiting embodiment, a device may be formed having a substrate that has at least a first region and a second region. The first region includes a memory region having at least one magnetic tunnel junction (MTJ) stack, and the second region includes a logic region. An encapsulation stack is formed in the first and second regions and over the MTJ stack(s). The encapsulation stack includes a first layer, a second layer, and a third layer. A single etch may remove at least a portion of the third layer, the second layer, and the first layer of the encapsulation stack to form a self-aligned MTJ via opening over the at least one MTJ stack to form one or more peaks from the encapsulation stack above or around the MTJ stack.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Yi Jiang, Juan Boon Tan
  • Patent number: 10566384
    Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Neha Nayyar, Curtis Chun-I Hsieh, Mahesh Bhatkar, Wenjun Liu, Juan Boon Tan
  • Publication number: 20200035906
    Abstract: A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.
    Type: Application
    Filed: July 26, 2018
    Publication date: January 30, 2020
    Inventors: Danny Pak-Chum SHUM, Wanbing YI, Curtis Chun-I HSIEH, Yi JIANG, Juan Boon TAN, Benfu LIN
  • Patent number: 10535645
    Abstract: A stitched device is disclosed. The stitched device includes first and second base devices having first and second stitched interconnects electrically coupled in a stitching level. This enables a single substrate of the stitched device to have electrically coupled first and second base devices.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: January 14, 2020
    Assignee: ALSEPHINA INNOVATIONS INC.
    Inventors: Wei Shao, Juan Boon Tan, Wei Liu, Wanbing Yi
  • Publication number: 20200013908
    Abstract: A semiconductor device having a substrate with at least one photo-detecting region and at least one bond pad is provided. A first passivation layer is deposited over the substrate and over step portions at the edges of the bond pad and a trench having sidewalls and a bottom surface is formed in the substrate. A light shielding layer is deposited over the first passivation layer and covering the trench sidewalls. The light shielding layer has end portions at the photo-detecting region, at step portions at the edges of the bond pad and at the bottom surface of the trench. A second passivation layer is deposited over the light shielding layer. A third passivation layer is deposited over the end portions of the light shielding layer at the photo-detecting region and at the step portions at edges of the bond pad.
    Type: Application
    Filed: July 4, 2018
    Publication date: January 9, 2020
    Inventors: WANBING YI, JUAN BOON TAN, KIOK BOONE ELGIN QUEK, KHEE YONG LIM, CHIM SENG SEET, RAJESH NAIR
  • Patent number: 10510946
    Abstract: Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetic random access memory (MRAM) chip magnetic shielding and methods of forming a magnetic shield processed at the wafer-level are disclosed. The method includes providing a magnetic shield at the front side of the chip, back side of the chip, and also in the deep trenches surrounding or adjacent to magnetic tunnel junction (MTJ) array within the prime die region. Magnetic shield in the deep trenches connects front side and back side magnetic shield. This magnetic shielding method is applicable for both in-plane and perpendicular MRAM chips. The MTJ array is formed in the prime die region and in between adjacent inter layer dielectric (ILD) levels of the upper ILD layer in the back end of line (BEOL) of the MRAM chip.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bharat Bhushan, Juan Boon Tan, Wanbing Yi, Danny Pak-Chum Shum, Shan Gao, Kangho Lee
  • Patent number: 10490745
    Abstract: Methods of forming planar RRAM and vertical RRAM with tip electrodes and the resulting devices are provided. Embodiments include forming a first metal oxide layer on a first dielectric layer; forming and patterning a mask layer over the first metal oxide layer; etching the first metal oxide through the mask layer to form openings for a first and second metal electrodes; removing the mask layer; forming the first and second metal electrodes in the openings; and forming a second metal oxide layer over the first and second metal electrodes, wherein the first and second metal electrodes are v-shaped in top view with tips of the first and second metal electrodes facing each other and a portion of the second metal oxide layer being formed between the tips of the first and second electrodes.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: November 26, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Jianxun Sun, Juan Boon Tan, Kwang Sing Yew, Wanbing Yi, Curtis Chun-I Hsieh, Tupei Chen
  • Patent number: 10483461
    Abstract: Method of forming embedded MRAM in interconnects using a metal hard mask process and the resulting device are provided. Embodiments include forming a first interlayer dielectric (ILD) layer including a first metal (Mx) level; forming a capping layer over the first ILD layer; forming magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer; forming a second metal (Mx+1) level in the second ILD layer; forming a second capping layer over the second ILD layer; and forming a third metal (Mx+2) level in a third ILD layer over the second capping layer.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: November 19, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Yi Jiang, Bharat Bhushan, Mahesh Bhatkar, Juan Boon Tan
  • Patent number: 10475990
    Abstract: Methods of forming a pillar contact extension within a memory device using a self-aligned planarization process rather than direct ILD CMP and the resulting devices are provided. Embodiments include forming a photoresist layer over a low-K layer formed over an ILD having a first metal layer in a memory region and in a logic region and pillar-shaped conductors formed atop of the first metal layer only in the memory region; forming a trench through the photoresist layer over each pillar-shaped conductor; extending the trench through the low-K layer to an upper surface of each pillar-shaped conductor; forming a second metal layer over the low-K layer, filling the trench entirely; and planarizing the second metal layer until the second metal layer is removed from over the logic region, a pillar contact extension formed atop of each pillar-shaped conductor.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Curtis Chun-I Hsieh, Lup San Leong, Wanbing Yi, Cing Gie Lim, Yi Jiang, Juan Boon Tan
  • Patent number: 10475985
    Abstract: Magnetic random access memory (MRAM) fan-out wafer level packages with package level and chip level magnetic shielding and methods of forming these magnetic shields processed at the wafer-level are disclosed. The method includes providing a MRAM wafer prepared with a plurality of MRAM dies. The MRAM wafer is processed to form a magnetic shield layer over the front side of the MRAM wafer, and the wafer is separated into a plurality of individual dies. An individual MRAM die includes front, back and lateral surfaces and the magnetic shield layer is disposed over the front surface of the MRAM die. Magnetic shield structures are provided over the individual MRAM dies. The magnetic shield structure encapsulates and surrounds back and lateral surfaces of the MRAM die. An encapsulation layer is formed to cover the individual MRAM dies which are provided with magnetic shield structures.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bharat Bhushan, Juan Boon Tan, Wanbing Yi, Pak-Chum Danny Shum
  • Publication number: 20190326509
    Abstract: Method of forming embedded MRAM in interconnects using a metal hard mask process and the resulting device are provided. Embodiments include forming a first interlayer dielectric (ILD) layer including a first metal (Mx) level; forming a capping layer over the first ILD layer; forming magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer; forming a second metal (Mx+1) level in the second ILD layer; forming a second capping layer over the second ILD layer; and forming a third metal (Mx+2) level in a third ILD layer over the second capping layer.
    Type: Application
    Filed: April 19, 2018
    Publication date: October 24, 2019
    Inventors: Wanbing YI, Curtis Chun-I HSIEH, Yi JIANG, Bharat BHUSHAN, Mahesh BHATKAR, Juan Boon TAN