Patents by Inventor Wanbing YI

Wanbing YI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190043922
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate having a buried insulator layer and an active layer overlying the buried insulator layer. A transistor overlies the buried insulator layer, and a memory cell underlies the buried insulator layer. As such, the memory cell and the transistor are on opposite sides of the buried insulator layer.
    Type: Application
    Filed: August 7, 2017
    Publication date: February 7, 2019
    Inventors: Bhushan Bharat, Juan Boon Tan, Danny Pak-Chum Shum, Yi Jiang, Wanbing Yi
  • Patent number: 10199572
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Yi Jiang, Daxiang Wang, Wei Shao, Juan Boon Tan
  • Patent number: 10170439
    Abstract: Devices are formed to have inner layers that have electronic devices, and an outer passivation layer. A patterned conductor is formed on a first surface of the inner layers, and through conductors (that extend through interior insulator layers) are positioned to electrically connect the patterned conductor to the electronic devices. The patterned conductor includes a pattern of connected linear sections that are parallel to the first surface of the inner layers. The linear sections of the patterned conductor meet at conductor corners, and at least one of the conductor corners of the patterned conductor includes a chamfer side that terminates at the linear sections. Further, the chamfer side is not perfectly diagonal, but instead forms unequal angles with the linear sections that intersect to form the corner.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ee Jan Khor, Juan Boon Tan, Wanbing Yi, Ramasamy Chockalingam, Qian Chen, Suleni Tunggal Mulia, Yongmei Hu
  • Patent number: 10158066
    Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: December 18, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Neha Nayyar, Curtis Chun-I Hsieh, Mahesh Bhatkar, Wenjun Liu, Juan Boon Tan
  • Publication number: 20180358546
    Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.
    Type: Application
    Filed: June 7, 2017
    Publication date: December 13, 2018
    Inventors: Wanbing YI, Neha NAYYAR, Curtis Chun-I HSIEH, Mahesh BHATKAR, Wenjun LIU, Juan Boon TAN
  • Publication number: 20180351078
    Abstract: Shielded semiconductor devices and methods for fabricating shielded semiconductor devices are provided. An exemplary magnetically shielded semiconductor device includes a substrate having a top surface and a bottom surface. An electromagnetic-field-susceptible semiconductor component is located on and/or in the substrate. The magnetically shielded semiconductor device includes a top magnetic shield located over the top surface of the substrate. Further, the magnetically shielded semiconductor device includes a bottom magnetic shield located under the bottom surface of the substrate. Also, the magnetically shielded semiconductor device includes a sidewall magnetic shield located between the top magnetic shield and the bottom magnetic shield.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventors: Bhushan Bharat, Shan Gao, Danny Pak-Chum Shum, Wanbing Yi, Juan Boon Tan, Wei Yi Lim, Teck Guan Lim, Michael Han Kim Kwong, Eva Wai Leong Ching
  • Publication number: 20180342556
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a capacitor, where the capacitor includes a first capacitor plate and a second capacitor plate. The first capacitor plate includes a first memory cell, and the second capacitor plate includes a second memory cell. The capacitor is utilized as a functional capacitor in the integrated circuit.
    Type: Application
    Filed: May 30, 2018
    Publication date: November 29, 2018
    Inventors: Juan Boon Tan, Mahesh Bhatkar, Bhushan Bharat, Wanbing Yi
  • Patent number: 10121755
    Abstract: A seal ring structure is disclosed for integrated circuit (IC) packaging. The seal ring includes an inner moisture barrier ring and an outer crack stop ring. Line structures of both the inner and outer rings include chamfered corners. The chamfers of a chamfered corner are devoid of acute angles. No metal line structure for the inner ring is provided at the pad level. The seal ring as described improves the reliability and strength of the structure and hence the seal ring can sustain high stress at the corners of the die during dicing.
    Type: Grant
    Filed: September 24, 2017
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Mahesh Bhatkar, Juan Boon Tan, Wanbing Yi
  • Patent number: 10096768
    Abstract: Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetic random access memory (MRAM) chip magnetic shielding at the device-level is disclosed. The MRAM chip includes a magnetic shield structure that is substantially surrounding a magnetic tunnel junction (MTJ) bit or device of a MTJ array. The magnetic shield may be configured in the form of a cylindrical shield structure or magnetic shield spacer that substantially surrounds the MTJ bit or device. The magnetic shield structure in the form of cylindrical shield structure or magnetic shield spacer may include top and/or bottom plate shield. The magnetic shield structure in various forms and configurations protect the MTJ stack from external or local magnetic fields. This magnetic shielding structure is applicable for both in-plane and perpendicular MRAM chips.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: October 9, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yi Jiang, Bharat Bhushan, Wanbing Yi, Juan Boon Tan, Pak-Chum Danny Shum
  • Patent number: 10062733
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a memory cell with a memory cell upper surface. A capping layer is formed overlying the memory cell, and a portion of the capping layer is removed to expose the memory cell upper surface. A memory cell etch stop is formed overlying the memory cell upper surface after the portion of the capping layer is removed to expose the memory cell upper surface. The memory cell etch stop is removed from overlying the memory cell upper surface, and an interconnect is formed in electrical communication with the memory cell.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 28, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Mahesh Bhatkar, Hui Liu, Chin Chuan Neo
  • Publication number: 20180233663
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first, second and third regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the first and second regions. A MRAM cell which includes a MTJ element sandwiched between top and bottom electrodes is formed in the second region. The bottom electrode is in direct contact with the metal line in the first upper interconnect level of the second region. A dielectric layer which includes a second upper interconnect level with a dual damascene interconnect in the first region and a damascene interconnect in the second region is provided over the first upper dielectric layer. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the damascene interconnect in the second region is coupled to the MTJ element.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 16, 2018
    Inventors: Danny Pak-Chum SHUM, Juan Boon TAN, Yi JIANG, Wanbing YI, Francis Yong Wee POH, Hai CONG
  • Publication number: 20180182810
    Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Inventors: Wanbing YI, Curtis Chun-I HSIEH, Juan Boon TAN, Soh Yun SIAH, Hai CONG, Alex SEE, Young Seon YOU, Danny Pak-Chum SHUM, Hyunwoo YANG
  • Publication number: 20180175284
    Abstract: Integrated circuits and methods for fabricating integrated circuits with magnetic tunnel junction (MTJ) structures are provided. An exemplary method for fabricating an integrated circuit includes forming an MTJ structure including a top electrode layer. The MTJ structure has a first sidewall and a second sidewall separated from the first sidewall by a first width. The method includes forming a conductive etch stop on the top electrode layer. The conductive etch stop has a second width greater than the first width. The method also includes depositing dielectric material over the conductive etch stop and the MTJ structure. The method further includes etching the dielectric material to form a trench exposing the conductive etch stop. Also, the method includes forming a conductive via in the trench over and in electrical communication with the conductive etch stop.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 21, 2018
    Inventors: Curtis Chun-I Hsieh, Wei-Hui Hsu, Wanbing Yi, Chim Seng Seet, Juan Boon Tan
  • Patent number: 9972775
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first, second and third regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the first and second regions. A MRAM cell which includes a MTJ element sandwiched between top and bottom electrodes is formed in the second region. The bottom electrode is in direct contact with the metal line in the first upper interconnect level of the second region. A dielectric layer which includes a second upper interconnect level with a dual damascene interconnect in the first region and a damascene interconnect in the second region is provided over the first upper dielectric layer. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the damascene interconnect in the second region is coupled to the MTJ element.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Juan Boon Tan, Yi Jiang, Wanbing Yi, Francis Yong Wee Poh, Hai Cong
  • Publication number: 20180090543
    Abstract: High density resistive memory structures, integrate circuits with high density resistive memory structures, and methods for fabricating high density resistive memory structures are provided. In an embodiment, a high density resistive memory structure includes a semiconductor substrate and a plurality of first electrodes in a first plane in and/or over the semiconductor substrate. Further, the high density resistive memory structure includes a plurality of second electrodes in a second plane in and/or over the semiconductor substrate. The second plane is parallel to the first plane, and each second electrode in the plurality of second electrodes crosses over or under each first electrode in the plurality of first electrodes at a series of cross points. Each second electrode in the plurality of second electrodes is non-linear and the series of cross points formed by each respective second electrode is non-linear.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 29, 2018
    Inventors: Curtis Chun-I Hsieh, Juan Boon Tan, Wanbing Yi, Yi Jiang
  • Patent number: 9917027
    Abstract: A method for fabricating an integrated circuit includes forming a first opening in an upper dielectric layer, the first opening having a first width, forming a second opening in a lower dielectric layer, the lower dielectric layer being below the upper dielectric layer, the second opening having a second width that is narrower than the first width, the second opening being substantially centered underneath the first opening so as to form a stepped via structure, conformally depositing an aluminum material layer in the stepped via structure and over the upper dielectric layer, and forming a passivation layer over the aluminum material layer.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: March 13, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Mahesh Bhatkar, Chin Chuan Neo, Juan Boon Tan
  • Patent number: 9905282
    Abstract: Methods of fabricating a dome-shaped MTJ TE and the resulting devices are provided. Embodiments include forming a MRAM stack having a laterally separated MTJ structures and the MRAM and a logic stack each having a SiN layer; forming first trenches through the MRAM stack to a portion of the SiN layer above an MTJ structure; forming second trenches through the SiN layer fully landing on an upper portion of the MTJ structures and removing the SiN layer of the logic stack; forming a TaN layer over the MRAM and logic stack; removing portions of the TaN layer on opposite sides of the MTJ structures and therebetween; forming an oxide layer over the MRAM and logic stacks; and forming vias through the oxide layer of the MRAM stack down the TaN layer above MTJ structures and a via through the logic stack.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: February 27, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Soh Yun Siah, Juan Boon Tan
  • Patent number: 9881844
    Abstract: An integrated circuit includes a copper hillock-detecting structure. The copper hillock-detecting structure includes a copper metallization layer and an intermediate plate structure spaced apart from adjacent to the copper metallization layer. The intermediate plate structure includes a conducting material plate. The intermediate plate structure further includes a plurality of conductive vias that are electrically and physically connected with the conducting material plate. The copper hillock-detecting structure further includes a sensing plate adjacent to the intermediate plate and electrically and physically connected with the plurality of vias such that the vias are disposed between the intermediate plate and the sensing plate.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: January 30, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Juan Boon Tan, Wei Shao, Gong Shun Qiang
  • Patent number: 9875971
    Abstract: Magnetic random access memory (MRAM) packages with magnetic shield protections and methods of forming thereof are presented. Package contact traces are formed on the first major surface of the package substrate and package balls are formed on the second major surface of the package substrate. A die having active and inactive surfaces is provided on the first major surface of the package substrate. The die includes a magnetic storage element, such as an array of magnetic tunnel junctions (MTJs), formed in the die, die microbumps formed on the active surface. The package includes a top magnetic shield layer formed on the inactive surface of the die. The package may also include a first bottom magnetic shield in the form of magnetic shield traces disposed below the package contact traces. The package may further include a second bottom magnetic shield in the form of magnetic permeable underfill dielectric material.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: January 23, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bharat Bhushan, Juan Boon Tan, Wanbing Yi
  • Patent number: 9865649
    Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions and providing a plurality of interlevel dielectric (ILD) levels having tight pitch over the first and second regions of the substrate. An ILD level of which a two-terminal element disposed thereon corresponds to a first ILD level and its metal level corresponds to Mx, an immediate ILD level overlying the metal level Mx corresponds to a second ILD level includes via level Vx and metal level Mx+1 and the next overlying ILD level corresponds to a third ILD level includes via level Vx+1 and metal level Mx+2. The method includes forming a two-terminal device element is formed in between metal level Mx and via level Vx+1 in the first region.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Juan Boon Tan, Wanbing Yi, Yi Jiang, Curtis Chun-I Hsieh, Danny Pak-Chum Shum