Patents by Inventor Wanbing YI

Wanbing YI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160351797
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.
    Type: Application
    Filed: May 26, 2016
    Publication date: December 1, 2016
    Inventors: Wanbing YI, Yi JIANG, Daxiang WANG, Wei SHAO, Juan Boon TAN
  • Publication number: 20160343610
    Abstract: A stitched device is disclosed. The stitched device includes first and second base devices having first and second stitched interconnects electrically coupled in a stitching level. This enables a single substrate of the stitched device to have electrically coupled first and second base devices.
    Type: Application
    Filed: May 18, 2015
    Publication date: November 24, 2016
    Inventors: Wei SHAO, Juan Boon TAN, Wei LIU, Wanbing YI
  • Patent number: 9490423
    Abstract: STT-MRAM integrated circuits employing aluminum metallization layers and methods for fabricating the same are disclosed. A method for fabricating an integrated circuit includes forming a first metallization layer including an aluminum material, forming a magnetic tunnel junction (MTJ) structure over the first metallization layer, and forming an encapsulation layer over the MTJ structure and over the first metallization layer. The method further includes etching the encapsulation layer and the first metallization layer to form an encapsulation segment overlying a first metal line, forming a contact plug to the MTJ structure, and forming a second metal line including an aluminum material over the contact plug.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: November 8, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Juan Boon Tan, Wanbing Yi, Danny Pak-Chum Shum
  • Patent number: 9466659
    Abstract: Wafer-level methods of forming circuit elements, such as multilayer inductors or transformers, are provided. The methods include, for instance: forming, in at least one layer above a substrate, at least one conductive portion of the circuit element; providing an uncured polymer-dielectric material surrounding, at least in part, and overlying the conductive portion(s) of the element; partially curing the polymer-dielectric material to obtain a partially-hardened, polymer-dielectric material; and polishing the partially-hardened, polymer-dielectric material down to the conductive portion(s). The polishing planarizes the partially-hardened, polymer-dielectric material and exposes an upper surface of the conductive portion(s) to facilitate forming at least one other conductive portion of the element above and in electrical contact with the conductive portion(s). After polishing, curing of the polymer-dielectric material is completed.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: October 11, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Luke England, Mahesh Anant Bhatkar, Wanbing Yi, Juan Boon Tan
  • Publication number: 20160284981
    Abstract: Magnetic random access memory (MRAM) packages with magnetic shield protections and methods of forming thereof are presented. Package contact traces are formed on the first major surface of the package substrate and package balls are formed on the second major surface of the package substrate. A die having active and inactive surfaces is provided on the first major surface of the package substrate. The die includes a magnetic storage element, such as an array of magnetic tunnel junctions (MTJs), formed in the die, die microbumps formed on the active surface. The package includes a top magnetic shield layer formed on the inactive surface of the die. The package may also include a first bottom magnetic shield in the form of magnetic shield traces disposed below the package contact traces. The package may further include a second bottom magnetic shield in the form of magnetic permeable underfill dielectric material.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 29, 2016
    Inventors: Bharat BHUSHAN, Juan Boon TAN, Wanbing YI
  • Publication number: 20160268336
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first, second and third regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the first and second regions. A MRAM cell which includes a MTJ element sandwiched between top and bottom electrodes is formed in the second region. The bottom electrode is in direct contact with the metal line in the first upper interconnect level of the second region. A dielectric layer which includes a second upper interconnect level with a dual damascene interconnect in the first region and a damascene interconnect in the second region is provided over the first upper dielectric layer. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the damascene interconnect in the second region is coupled to the MTJ element.
    Type: Application
    Filed: March 8, 2016
    Publication date: September 15, 2016
    Inventors: Danny Pak-Chum SHUM, Juan Boon TAN, Yi JIANG, Wanbing YI, Francis Yong Wee POH, Hai CONG
  • Patent number: 9397139
    Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first upper dielectric layer is provided over the substrate. The first upper dielectric layer comprises a first upper interconnect level with a plurality of metal lines. A dielectric layer is formed over the first upper dielectric layer. The dielectric layer includes a second upper interconnect level with a plurality of metal lines. A magnetic random access memory (MRAM) cell is formed between the first and second upper interconnect levels in the first region. An inductor is formed in the second region. The inductor includes a lower inductor level formed from metal lines in the first upper interconnect level and an upper inductor level formed from metal lines in the second upper interconnect level. The metal lines in the lower inductor level and upper inductor level are coupled by via contacts to form loops of the inductor.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: July 19, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Juan Boon Tan, Yi Jiang, Wanbing Yi, Danny Pak-Chum Shum
  • Publication number: 20160189971
    Abstract: A semiconductor device and method for forming a semiconductor device are presented. The method includes providing a patterned reticle having a pattern perimeter defined by active and dummy patterns. The dummy patterns include dummy structures modified according to a density equation. The patterned reticle is used to pattern a resist layer on a substrate with a device layer. An etch is performed to pattern the device layer using the patterned resist layer. Additional processing is performed to complete formation of the device.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 30, 2016
    Inventors: Wanbing Yi, Chin Chuan Neo, Hai Cong, Kin Wai Tang, Weining Li, Juan Boon Tan
  • Patent number: 9349772
    Abstract: A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and within a trench of the passivation layer and removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing. The method further includes forming a further passivation layer over the MTJ/top electrode stack, forming a further ILD layer of the further passivation layer, and reforming a top electrode layer over the ILD layer and over the MTJ/top electrode stack. Still further, the method includes removing portions of the bottom electrode layer, the further passivation layer, the further ILD layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 24, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Yang Hong, Yi Jiang, Francis Poh, Tze Ho Simon Chan, Juan Boon Tan
  • Patent number: 9343662
    Abstract: A device and a method of forming a device are presented. A substrate is provided. Front end of line processing is performed to form circuit component on the substrate and back end of line processing is performed to include the uppermost inter level dielectric (ILD) layer. The uppermost ILD layer includes first and second interconnects. A pad level is formed over the uppermost ILD layer. A storage unit of a memory cell is provided in the pad level. The storage unit is coupled to the first interconnect of the uppermost ILD layer. A cell interconnect and a pad interconnect are formed in the pad level. The cell interconnect is formed on top of and coupled to the storage unit and the pad interconnect is coupled to the second interconnect in the uppermost ILD layer.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: May 17, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Juan Boon Tan, Wanbing Yi, Danny Pak-Chum Shum, Yi Jiang
  • Publication number: 20160133565
    Abstract: Magnetic core inductors implemented on integrated circuits and methods for fabricating such magnetic core inductors are disclosed. An exemplary magnetic core inductor includes a bottom magnetic plate that includes a center portion and first, second, third, and fourth extension portions extending from the center portion. The exemplary magnetic core inductor includes an interlayer dielectric layer disposed over the bottom magnetic plate, and within the interlayer dielectric layer, first, second, third, and fourth via trenches extending above a respective one of the first, second, third, and fourth extension portions, and a fifth via trench extending above the center portion. The magnetic core inductor further includes a stacked-ring inductor coil including a plurality of inductor rings surrounding the fifth via trench and a top magnetic plate including a center portion and first, second, third, and fourth extension portions extending from the center portion.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 12, 2016
    Inventors: Mahesh Bhatkar, Lulu Peng, Wanbing Yi, Juan Boon Tan, Luke England
  • Publication number: 20160133531
    Abstract: Embodiments of a method for forming a device using test structures are presented. The method includes providing a wafer with a device layer. The device layer includes a main device region and a perimeter region. The device layer is patterned with active and test patterns. Test patterns include dummy patterns disposed in a test device area. The wafer is processed to form at least one test device disposed in the perimeter region and one or more active devices disposed in the main device region. The test device determines a design window of the one or more active devices. Additional processing is performed to complete forming the device.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 12, 2016
    Inventors: Wanbing YI, Daxiang WANG, Juan Boon TAN, Kemao LIN, Shaoqiang ZHANG
  • Publication number: 20160133830
    Abstract: STT-MRAM integrated circuits employing aluminum metallization layers and methods for fabricating the same are disclosed. A method for fabricating an integrated circuit includes forming a first metallization layer including an aluminum material, forming a magnetic tunnel junction (MTJ) structure over the first metallization layer, and forming an encapsulation layer over the MTJ structure and over the first metallization layer. The method further includes etching the encapsulation layer and the first metallization layer to form an encapsulation segment overlying a first metal line, forming a contact plug to the MTJ structure, and forming a second metal line including an aluminum material over the contact plug.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 12, 2016
    Inventors: Juan Boon Tan, Wanbing Yi, Danny Pak-Chum Shum
  • Publication number: 20160118355
    Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 28, 2016
    Inventors: Benfu LIN, Wanbing YI, Wei LU, Alex SEE, Juan Boon TAN
  • Publication number: 20160093670
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with a memory cell region. A first upper dielectric layer is provided over the substrate. The first upper dielectric layer includes a first upper interconnect level with one or more metal lines in the memory cell region. A second upper dielectric layer is provided over the first upper dielectric layer. The second upper dielectric layer includes a via plug coupled to the metal line of the first upper interconnect level. An alignment trench which extends from a top surface of the second upper dielectric layer to a portion of the second upper dielectric layer is formed. Various layers of a MTJ stack are formed over the second upper dielectric layer. Profile of the alignment trench is transferred to surfaces of the various layers of the MTJ stack to form a topography feature which serves as an alignment mark.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 31, 2016
    Inventors: Yi JIANG, Wanbing YI, Juan Boon TAN, Danny Pak-Chum SHUM
  • Patent number: 9240374
    Abstract: Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate prepared with intermediate dielectric layer having interconnect levels. The interconnect levels include M1 to MX metal levels, where 1 is the lowest level and X corresponds to a number of metal level. The metal level MX includes a metal pad having an oxidized portion. An upper level having an upper dielectric layer is formed over the dielectric layer having MX. The upper dielectric layer includes a plurality of via contacts over the metal pad and a metal line over the via contacts. The oxidized portion remains within the metal pad and prevents punch through between MX and its adjacent underlying metal level MX-1.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: January 19, 2016
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Wei Shao, Wanbing Yi, Shunqiang Gong, Chao Zhu, Juan Boon Tan
  • Publication number: 20160013262
    Abstract: Wafer-level methods of forming circuit elements, such as multilayer inductors or transformers, are provided. The methods include, for instance: forming, in at least one layer above a substrate, at least one conductive portion of the circuit element; providing an uncured polymer-dielectric material surrounding, at least in part, and overlying the conductive portion(s) of the element; partially curing the polymer-dielectric material to obtain a partially-hardened, polymer-dielectric material; and polishing the partially-hardened, polymer-dielectric material down to the conductive portion(s). The polishing planarizes the partially-hardened, polymer-dielectric material and exposes an upper surface of the conductive portion(s) to facilitate forming at least one other conductive portion of the element above and in electrical contact with the conductive portion(s). After polishing, curing of the polymer-dielectric material is completed.
    Type: Application
    Filed: July 9, 2014
    Publication date: January 14, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Luke ENGLAND, Mahesh Anant BHATKAR, Wanbing YI, Juan Boon TAN
  • Publication number: 20150311251
    Abstract: A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and within a trench of the passivation layer and removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing. The method further includes forming a further passivation layer over the MTJ/top electrode stack, forming a further ILD layer of the further passivation layer, and reforming a top electrode layer over the ILD layer and over the MTJ/top electrode stack. Still further, the method includes removing portions of the bottom electrode layer, the further passivation layer, the further ILD layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack.
    Type: Application
    Filed: April 25, 2014
    Publication date: October 29, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: WANBING YI, YANG HONG, YI JIANG, Francis Poh, Tze Ho Simon Chan, Juan Boon Tan
  • Patent number: 9111941
    Abstract: Memory devices and methods for forming the device are disclosed. The device includes a substrate having an array surface and a non-array surface and a memory array having a plurality of memory cells interconnected by first conductors in a first direction and second conductors in a second direction. The memory array is disposed on the array surface of the substrate. The device further includes through silicon via (TSV) contacts disposed in the substrate. The TSV contacts extend from the array surface to the non-array surface, enabling electrical connections to the array from the non-array surface.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: August 18, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shunqiang Gong, Juan Boon Tan, Lei Wang, Wei Liu, Wanbing Yi, Jens Oswald
  • Publication number: 20150187700
    Abstract: Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate prepared with intermediate dielectric layer having interconnect levels. The interconnect levels include M1 to MX metal levels, where 1 is the lowest level and X corresponds to a number of metal level. The metal level MX includes a metal pad having an oxidized portion. An upper level having an upper dielectric layer is formed over the dielectric layer having MX. The upper dielectric layer includes a plurality of via contacts over the metal pad and a metal line over the via contacts. The oxidized portion remains within the metal pad and prevents punch through between MX and its adjacent underlying metal level MX-1.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 2, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Wei SHAO, Wanbing YI, Shunqiang GONG, Chao ZHU, Juan Boon TAN