Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first upper dielectric layer is provided over the substrate. The first upper dielectric layer comprises a first upper interconnect level with a plurality of metal lines. A dielectric layer is formed over the first upper dielectric layer. The dielectric layer includes a second upper interconnect level with a plurality of metal lines. A magnetic random access memory (MRAM) cell is formed between the first and second upper interconnect levels in the first region. An inductor is formed in the second region. The inductor includes a lower inductor level formed from metal lines in the first upper interconnect level and an upper inductor level formed from metal lines in the second upper interconnect level. The metal lines in the lower inductor level and upper inductor level are coupled by via contacts to form loops of the inductor.

Abstract: A semiconductor device and method for forming a semiconductor device are presented. The method includes providing a patterned reticle having a pattern perimeter defined by active and dummy patterns. The dummy patterns include dummy structures modified according to a density equation. The patterned reticle is used to pattern a resist layer on a substrate with a device layer. An etch is performed to pattern the device layer using the patterned resist layer. Additional processing is performed to complete formation of the device.

Abstract: A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and within a trench of the passivation layer and removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing. The method further includes forming a further passivation layer over the MTJ/top electrode stack, forming a further ILD layer of the further passivation layer, and reforming a top electrode layer over the ILD layer and over the MTJ/top electrode stack. Still further, the method includes removing portions of the bottom electrode layer, the further passivation layer, the further ILD layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack.

Abstract: A device and a method of forming a device are presented. A substrate is provided. Front end of line processing is performed to form circuit component on the substrate and back end of line processing is performed to include the uppermost inter level dielectric (ILD) layer. The uppermost ILD layer includes first and second interconnects. A pad level is formed over the uppermost ILD layer. A storage unit of a memory cell is provided in the pad level. The storage unit is coupled to the first interconnect of the uppermost ILD layer. A cell interconnect and a pad interconnect are formed in the pad level. The cell interconnect is formed on top of and coupled to the storage unit and the pad interconnect is coupled to the second interconnect in the uppermost ILD layer.

Abstract: Magnetic core inductors implemented on integrated circuits and methods for fabricating such magnetic core inductors are disclosed. An exemplary magnetic core inductor includes a bottom magnetic plate that includes a center portion and first, second, third, and fourth extension portions extending from the center portion. The exemplary magnetic core inductor includes an interlayer dielectric layer disposed over the bottom magnetic plate, and within the interlayer dielectric layer, first, second, third, and fourth via trenches extending above a respective one of the first, second, third, and fourth extension portions, and a fifth via trench extending above the center portion. The magnetic core inductor further includes a stacked-ring inductor coil including a plurality of inductor rings surrounding the fifth via trench and a top magnetic plate including a center portion and first, second, third, and fourth extension portions extending from the center portion.

Abstract: Embodiments of a method for forming a device using test structures are presented. The method includes providing a wafer with a device layer. The device layer includes a main device region and a perimeter region. The device layer is patterned with active and test patterns. Test patterns include dummy patterns disposed in a test device area. The wafer is processed to form at least one test device disposed in the perimeter region and one or more active devices disposed in the main device region. The test device determines a design window of the one or more active devices. Additional processing is performed to complete forming the device.

Abstract: STT-MRAM integrated circuits employing aluminum metallization layers and methods for fabricating the same are disclosed. A method for fabricating an integrated circuit includes forming a first metallization layer including an aluminum material, forming a magnetic tunnel junction (MTJ) structure over the first metallization layer, and forming an encapsulation layer over the MTJ structure and over the first metallization layer. The method further includes etching the encapsulation layer and the first metallization layer to form an encapsulation segment overlying a first metal line, forming a contact plug to the MTJ structure, and forming a second metal line including an aluminum material over the contact plug.

Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.

Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with a memory cell region. A first upper dielectric layer is provided over the substrate. The first upper dielectric layer includes a first upper interconnect level with one or more metal lines in the memory cell region. A second upper dielectric layer is provided over the first upper dielectric layer. The second upper dielectric layer includes a via plug coupled to the metal line of the first upper interconnect level. An alignment trench which extends from a top surface of the second upper dielectric layer to a portion of the second upper dielectric layer is formed. Various layers of a MTJ stack are formed over the second upper dielectric layer. Profile of the alignment trench is transferred to surfaces of the various layers of the MTJ stack to form a topography feature which serves as an alignment mark.

Abstract: Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate prepared with intermediate dielectric layer having interconnect levels. The interconnect levels include M1 to MX metal levels, where 1 is the lowest level and X corresponds to a number of metal level. The metal level MX includes a metal pad having an oxidized portion. An upper level having an upper dielectric layer is formed over the dielectric layer having MX. The upper dielectric layer includes a plurality of via contacts over the metal pad and a metal line over the via contacts. The oxidized portion remains within the metal pad and prevents punch through between MX and its adjacent underlying metal level MX-1.

Abstract: Wafer-level methods of forming circuit elements, such as multilayer inductors or transformers, are provided. The methods include, for instance: forming, in at least one layer above a substrate, at least one conductive portion of the circuit element; providing an uncured polymer-dielectric material surrounding, at least in part, and overlying the conductive portion(s) of the element; partially curing the polymer-dielectric material to obtain a partially-hardened, polymer-dielectric material; and polishing the partially-hardened, polymer-dielectric material down to the conductive portion(s). The polishing planarizes the partially-hardened, polymer-dielectric material and exposes an upper surface of the conductive portion(s) to facilitate forming at least one other conductive portion of the element above and in electrical contact with the conductive portion(s). After polishing, curing of the polymer-dielectric material is completed.

Abstract: Memory devices and methods for forming the device are disclosed. The device includes a substrate having an array surface and a non-array surface and a memory array having a plurality of memory cells interconnected by first conductors in a first direction and second conductors in a second direction. The memory array is disposed on the array surface of the substrate. The device further includes through silicon via (TSV) contacts disposed in the substrate. The TSV contacts extend from the array surface to the non-array surface, enabling electrical connections to the array from the non-array surface.

Abstract: Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate prepared with intermediate dielectric layer having interconnect levels. The interconnect levels include M1 to MX metal levels, where 1 is the lowest level and X corresponds to a number of metal level. The metal level MX includes a metal pad having an oxidized portion. An upper level having an upper dielectric layer is formed over the dielectric layer having MX. The upper dielectric layer includes a plurality of via contacts over the metal pad and a metal line over the via contacts. The oxidized portion remains within the metal pad and prevents punch through between MX and its adjacent underlying metal level MX-1.

Abstract: Integrated circuits with copper hillock-detecting structures and methods for detecting copper hillocks using the same are disclosed. In an exemplary embodiment, an integrated circuit includes a copper hillock-detecting structure. The copper hillock-detecting structure includes a copper metallization layer and an intermediate plate structure adjacent to the copper metallization layer. The intermediate plate structure includes a conducting material plate. The intermediate plate structure further includes a plurality of vias electrically and physically connected with the conducting material plate. The copper hillock-detecting structure further includes a sensing plate adjacent to the intermediate plate and electrically and physically connected with the plurality of vias.

Abstract: A device and a method of forming a device are presented. A substrate is provided. Front end of line processing is performed to form circuit component on the substrate and back end of line processing is performed to include the uppermost inter level dielectric (ILD) layer. The uppermost ILD layer includes first and second interconnects. A pad level is formed over the uppermost ILD layer. A storage unit of a memory cell is provided in the pad level. The storage unit is coupled to the first interconnect of the uppermost ILD layer. A cell interconnect and a pad interconnect are formed in the pad level. The cell interconnect is formed on top of and coupled to the storage unit and the pad interconnect is coupled to the second interconnect in the uppermost ILD layer.

Abstract: A bonding pad and a method of manufacturing a bonding pad are presented. The method includes providing a substrate prepared with circuits component and an interlevel dielectric (ILD) layer with interconnects. A final passivation level is formed on the substrate surface and includes a pad opening. A wire bond in contact with the pad interconnect is formed in the pad opening. The pad interconnect is suitable for, for example, copper wire bond and can avoid the formation of intermetallic compound during wire bonding. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Memory devices and methods for forming the device are disclosed. The device includes a substrate having an array surface and a non-array surface and a memory array having a plurality of memory cells interconnected by first conductors in a first direction and second conductors in a second direction. The memory array is disposed on the array surface of the substrate. The device further includes through silicon via (TSV) contacts disposed in the substrate. The TSV contacts extend from the array surface to the non-array surface, enabling electrical connections to the array from the non-array surface.