Abstract: A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be in a conductive state.

Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.

Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may turned on while the pMOSFET is turned off. The nMOSFET provides a higher resistance in place of the decreased resistance of the pMOSFET to amplify a signal at a sense circuit to allow accurate sensing of the voltage across the memory cell.

Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be turned on while the pMOSFET remains on. The nMOSFET adds a resistance which offsets a decreased resistance of the pMOSFET to allow accurate sensing of the voltage across the memory cell.

Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test.

Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be turned on while the pMOSFET remains on. The nMOSFET adds a resistance which offsets a decreased resistance of the pMOSFET to allow accurate sensing of the voltage across the memory cell.

Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may turned on while the pMOSFET is turned off. The nMOSFET provides a higher resistance in place of the decreased resistance of the pMOSFET to amplify a signal at a sense circuit to allow accurate sensing of the voltage across the memory cell.

Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM device, is connected in series with a threshold switching selector, such as an ovonic threshold switch. In a two-layer cross-point structure with such memory cells, the MRAM devices in one layer are inverted relative to the MRAM devices in the other layer. This can allow for the transient voltage spike placed across the MRAM device when the threshold switching selector first turns on in a sensing operation to dissipate more rapidly, reducing the risk of changing a stored data state before it can be sensed.

Abstract: Apparatuses and techniques are described for reading crosspoint arrays of memory cells with high bandwidth and a relatively small page buffer. Multiple crosspoint arrays (XPAs) are read in parallel, with one memory cell per XPA being read, in a bank of XPAs. To reduce the read time, a row can be selected for the XPAs, after which memory cells in different columns are read, one column at a time, while the same row is selected. This avoids the need to transmit commands and a row address for re-selecting the row in each successive read operation. The XPAs may be ungrouped, or one XPA may be accessible at a time in a group. In one option, the XPAs are arranged in sets, either individually or in groups, and one set is accessible at a time.

Abstract: Apparatuses and techniques are described for reading crosspoint arrays of memory cells with high bandwidth and a relatively small page buffer. Multiple crosspoint arrays (XPAs) are read in parallel, with one memory cell per XPA being read, in a bank of XPAs. To reduce the read time, a row can be selected for the XPAs, after which memory cells in different columns are read, one column at a time, while the same row is selected. This avoids the need to transmit commands and a row address for re-selecting the row in each successive read operation. The XPAs may be ungrouped, or one XPA may be accessible at a time in a group. In one option, the XPAs are arranged in sets, either individually or in groups, and one set is accessible at a time.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for data rewrite operations. A non-volatile memory device comprises a non-volatile memory medium. A non-volatile memory device is configured to determine an error metric for a non-volatile memory medium in response to a read request for the non-volatile memory medium. A non-volatile memory device is configured to receive a refresh command from a controller over a bus. A non-volatile memory device is configured to rewrite data from a non-volatile memory medium during a predefined time period after receiving a refresh command in response to an error metric satisfying an error threshold.

Abstract: A method of operating a phase change memory device includes flowing a write current of a first polarity through a phase change memory element of a selected phase change memory cell, and flowing a read current of a second polarity opposite to the first polarity through the phase change memory element of the selected phase change memory cell. A first junction between the phase change memory element and a first electrode and a second junction between the phase change memory element and a second electrode exhibit asymmetric thermoelectric heat generation during the step of flowing the write current.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for memory maintenance operations. A non-volatile memory device comprises a non-volatile memory medium. A non-volatile memory device is configured to receive a refresh command from a controller over a bus. A non-volatile memory device is configured to perform one or more maintenance operations on a non-volatile memory medium during a predefined period of time after receiving a refresh command.

Abstract: A method of operating a phase change memory device includes flowing a write current of a first polarity through a phase change memory element of a selected phase change memory cell, and flowing a read current of a second polarity opposite to the first polarity through the phase change memory element of the selected phase change memory cell. A first junction between the phase change memory element and a first electrode and a second junction between the phase change memory element and a second electrode exhibit asymmetric thermoelectric heat generation during the step of flowing the write current.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for memory array addressing. An addressing circuit is configured to receive an address for an operation on an array of multiple memory regions. An address includes a row address and a column address both multiplexed into the address and received with an activate command for an operation. A row buffer for an array of multiple memory regions is configured to store data identified by multiplexed row and column addresses from the multiple memory regions. Data of an operation is selected from a row buffer based on a second address received with a subsequent command for the operation.

Abstract: In a memory system, variable resistance circuits, such as transistor circuits, in the word line and bit line decoders are set during bias line set times and/or prior to turn-on times of read operations to increased resistance levels. The variable resistance circuits are kept at the increased resistance levels during an initial turn-on time period during which a selected memory cell may conducts a current spike. The increased resistance levels of the variable resistance circuit may operate to reduce or limit the width of the current spike. In response to the initial turn-on time period ending, the variable resistance circuits are set back to low resistance levels to facilitate subsequent sense results detection events and program operations.

Abstract: In a memory system, variable resistance circuits, such as transistor circuits, in the word line and bit line decoders are set during bias line set times and/or prior to turn-on times of read operations to increased resistance levels. The variable resistance circuits are kept at the increased resistance levels during an initial turn-on time period during which a selected memory cell may conducts a current spike. The increased resistance levels of the variable resistance circuit may operate to reduce or limit the width of the current spike. In response to the initial turn-on time period ending, the variable resistance circuits are set back to low resistance levels to facilitate subsequent sense results detection events and program operations.

Abstract: Apparatuses and techniques are described for programming phase change memory cells while avoiding a clamp condition in transistors which are used for biasing a word line and bit line when the word line and bit line are unselected for a write operation. The transistors may be connected in parallel with the word line and bit line. During a write operation, a current source is connected to a selected word line and a voltage control circuit is connected to the selected bit line. The voltage control circuit can include a capacitor or a voltage driver, for example. The capacitor accumulates charge, or the voltage driver applies an increasing ramp voltage to the bit line, to increase the voltage of the bit line and word line during the write operation and to avoid the clamp condition.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for data rewrite operations. A non-volatile memory device comprises a non-volatile memory medium. A non-volatile memory device is configured to determine an error metric for a non-volatile memory medium in response to a read request for the non-volatile memory medium. A non-volatile memory device is configured to receive a refresh command from a controller over a bus. A non-volatile memory device is configured to rewrite data from a non-volatile memory medium during a predefined time period after receiving a refresh command in response to an error metric satisfying an error threshold.