Abstract: An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.

Abstract: A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory element. The programmable resistance memory may be a phase change memory. The feedback control circuit monitors and controls the characteristics of a current pulse employed to program a memory cell.

Abstract: A three-dimensional memory array formed of one or more two-dimensional memory arrays of one-time programmable memory elements arranged in horizontal layers and stacked vertically upon one another; and a two-dimensional memory array of reprogrammable phase change memory elements stacked on the one or more two-dimensional memory arrays as the top layer of the three-dimensional memory array.

Abstract: Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb.

Abstract: A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory element. The programmable resistance memory may be a phase change memory. The feedback control circuit monitors and controls the characteristics of a current pulse employed to program a memory cell.

Abstract: An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.

Abstract: A random access memory device is disclosed having an interface that is compatible with a NAND FLASH memory device such that the device can be operated with a standard NAND memory device's controller device. This memory device is can store data internally using any random access storage technology including PRAM, MRAM, RRAM, FRAM, OTP-RAM and 3-D memory.

Abstract: A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory element. The programmable resistance memory may be a phase change memory. The feedback control circuit monitors and controls the characteristics of a current pulse employed to program a memory cell.

Abstract: An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.

Abstract: A memory element, a threshold switching element, or the series combination of a memory element and a threshold switching element may be used for coupling conductive lines in an electrically programmable matrix array. Leakage may be reduced by optionally placing a breakdown layer in series with the phase-change material and/or threshold switching material between the conductive lines. The matrix array may be used in a programmable logic device.

Abstract: A three-dimensional memory array formed of one or more two-dimensional memory arrays of one-time programmable memory elements arranged in horizontal layers and stacked vertically upon one another; and a two-dimensional memory array of reprogrammable phase change memory elements stacked on the one or more two-dimensional memory arrays as the top layer of the three-dimensional memory array.

Abstract: A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller.

Abstract: A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller.

Abstract: A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller.

Abstract: A memory is configurable among a plurality of operational modes. The operational modes may dictate the number of storage levels to be associated with each cell within the memory's storage matrix.

Abstract: A bidirectional memory cell includes an ovonic threshold switch (OTS) and a bidirectional memory element. The OTS is configured to select the bidirectional memory element and to prevent inadvertent accesses to the memory element.

Abstract: A rewritable nonvolatile memory includes a test cell that is dedicated to testing the storage characteristics of other, similar, storage cells formed within the same integrated circuit memory. The test cell may be share the same structure and composition as storage cells and may be positioned proximate storage cells.

Abstract: An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.

Abstract: A random access memory device is disclosed having an interface that is compatible with a NAND FLASH memory device such that the device can be operated with a standard NAND memory device's controller device. This memory device is can store data internally using any random access storage technology including PRAM, MRAM, RRAM, FRAM, OTP-RAM and 3-D memory.

Abstract: A memory employs a low-level current source to access a phase change memory cell. The current source charges an access capacitor in order to store sufficient charge for an ensuing access. When a memory cell is accessed, charge stored on the capacitor is discharged through the phase change memory, supplying a current to the phase change memory cell that is sufficient for the intended access operation and greater than that provided directly by the current source.