Abstract: A phase-change material is proposed for coupling interconnect lines an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer between the phase change material and at least one of the lines. The matrix array may be used in a programmable logic device. The logic portions of the programmable logic device may be tri-stated.

Abstract: A phase change memory may be utilized in place of a dynamic random access memory in a processor-based system. The memory may keep track of the number of read or write cycles so that it may determine when a refresh cycle will occur. During the refresh cycle, the phase change memory may implement other tasks not related to a refresh because the phase change memory does not need to be refreshed. Typical of such tasks may be determining whether any bits are weakly programmed or improperly programmed and taking corrective action with respect to those bits.

Abstract: A one time programmable phase change memory may include an array of phase change memory cells. Because the array is one time programmable, users may provide the manufacturer with code to be pre-programmed into the array. The memory may be programmed, for example, by fusing one or more cells to exhibit the desired memory state.

Abstract: A phase change memory may be utilized to replace NAND flash memory in combination with a buffer such as a static random access memory and/or a dynamic random access memory. Because the phase change memory may have sufficiently low cost, it may replace low cost NAND flash and because the phase change memory has sufficiently high performance, it can also replace the dynamic random access or static random access buffer memory sometimes packaged with the NAND flash memory. Thus, a relatively low cost, high performance solution is achieved in a relatively small package size in some embodiments.

Abstract: A phase change memory may be utilized in place of more conventional, higher volume memories such as static random access memory, flash memory, or dynamic random access memory. To account for the fact that the phase change memory is not yet a high volume technology, an error correcting code may be incorporated. The error correcting code may be utilized in ways which do not severely negatively impact read access times, in some embodiments.

Abstract: A memory may include a phase change memory element and series connected first and second selection devices. The second selection device may have a higher resistance and a larger threshold voltage than the first selection device. In one embodiment, the first selection device may have a threshold voltage substantially equal to its holding voltage. In some embodiments, the selection devices and the memory element may be made of chalcogenide. In some embodiments, the selection devices may be made of non-programmable chalcogenide. The selection device with the higher threshold voltage may contribute lower leakage to the combination, but may also exhibit increased snapback. This increased snapback may be counteracted by the selection device with the lower threshold voltage, resulting in a combination with low leakage and high performance in some embodiments.

Abstract: An analog memory may be formed using a phase change material. The phase change material may assume one of a number of resistance states which defines a specific analog characteristic to be stored.

Abstract: A read bias scheme may be used for phase change memories including a chalcogenide access device and a chalcogenide memory element. Through an appropriate read bias scheme, desirable read margin can be achieved. This may result in better yield, higher reliability, and ultimately lower costs in some cases.

Abstract: A driver circuit having one or more MOS transistors. The driver circuit is capable of providing an output voltage greater than the power supply voltage; however, the magnitude of the voltages appearing across the terminals of the MOS transistors are preferably less than or equal to the magnitude of the power supply voltage. The driver circuit may comprise a plurality of serially coupled PMOS transistors and a plurality of serially coupled NMOS transistors wherein the plurality of PMOS transistors and plurality of NMOS transistors are coupled at the output node of the driver.

Abstract: A method of programming a programmable resistance element. The programmable resistance element may be programmed to a BLOWN state. After being programmed to the BLOWN state, the element can no longer be programmed to its low resistance state. The method of programming allows the programmable resistance element to be used as a fuse.

Abstract: A phase change memory may be made using an isolation diode in the form of a Schottky diode between a memory cell and a word line. The use of Schottky diode isolation devices may make the memory more scaleable in some embodiments.

Abstract: A method of programming a programmable resistance element. The programmable resistance element may be programmed to a BLOWN state. After being programmed to the BLOWN state, the element can no longer be programmed to its low resistance state. The method of programming allows the programmable resistance element to be used as a fuse.

Abstract: A driver circuit having one or more MOS transistors. The driver circuit is capable of providing an output voltage greater than the power supply voltage; however, the magnitude of the voltages appearing across the terminals of the MOS transistors are preferably less than or equal to the magnitude of the power supply voltage. The driver circuit may comprise a plurality of serially coupled PMOS transistors and a plurality of serially coupled NMOS transistors wherein the plurality of PMOS transistors and plurality of NMOS transistors are coupled at the output node of the driver.

Abstract: A memory device includes an array of memory cells arranged in rows and columns. A row-address decoder allows a row address to propagate therethrough while a row address strobe is at an inactive logic level. In response to a transition of the row address strobe from the inactive level to an active level, the decoder enables a row of memory cells selected by the row address. A row-address latch stores the row address in response to the transition of the row address strobe. The memory device may also include a transition detector that monitors the row address for a transition thereof. A delay circuit is coupled to the decoder, the latch, and the detector. If the monitor detects a transition of the row address, the delay circuit delays the enabling of the row of memory cells and the storing of the row address at least predetermined time after such a transition.

Abstract: A memory device includes an array of memory cells arranged in rows and columns. A row-address decoder allows a row address to propagate therethrough while a row address strobe is at an inactive logic level. In response to a transition of the row address strobe from the inactive level to an active level, the decoder enables a row of memory cells selected by the row address. A row-address latch stores the row address in response to the transition of the row address strobe. The memory device may also include a transition detector that monitors the row address for a transition thereof. A delay circuit is coupled to the decoder, the latch, and the detector. If the monitor detects a transition of the row address, the delay circuit delays the enabling of the row of memory cells and the storing of the row address at least predetermined time after such a transition.

Abstract: A memory device includes an array of memory cells arranged in rows and columns. A row-address decoder allows a row address to propagate therethrough while a row address strobe is at an inactive logic level. In response to a transition of the row address strobe from the inactive level to an active level, the decoder enables a row of memory cells selected by the row address. A row-address latch stores the row address in response to the transition of the row address strobe. The memory device may also include a transition detector that monitors the row address for a transition thereof. A delay circuit is coupled to the decoder, the latch, and the detector. If the monitor detects a transition of the row address, the delay circuit delays the enabling of the row of memory cells and the storing of the row address at least predetermined time after such a transition.

Abstract: The present invention relates to an integrated circuit device particularly of the type carrying multiple memory circuits or the like. The device incorporates a lead frame of the sort which includes an elongate metallic web and is characterized by the lead frame providing an integral seat or platform whereon is mounted a capacitor device which is connected or adapted to be connected in shunting relation of the power supply inputs to the integrated circuit device, whereby the capacitor provides a convenient mounting platform for the circuit bearing elements and also assures minimal lead lengths between the capacitor and the power supply inputs of the circuit bearing chip. Due to the shortness of such lead lengths and consequent reduction of the inductance reactance of the power supply circuit, efficient dampening of switching transients is achieved with the use of capacitors of much smaller values, in less area than heretofore required in external dampening applications.

Abstract: The present invention is directed to an integrated circuit device comprising a lead frame having a ceramic capacitor mounted thereon and forming the support for a silicon chip bearing a multiplicity of circuits, including at least two power supply circuits namely a main power supply circuit and a secondary circuit. The capacitor is shunted across the terminals of the main power supply and the main power terminals of said IC chip. A conductive layer disposed atop the ceramic uppermost layer of the capacitor defines with the uppermost electrode of the capacitor, a second capacitive load of lesser value than the main capacitor, the said second capacitive load being shunted across the terminals of the secondary power supply and a secondary set of power terminals of said chip.

Abstract: The present invention is directed to an IC device of the ceramic encapsulated type wherein a power supply pulse dampening capacitor is embodied within the IC housing. The device is characterized by the utilization of a chip capacitor bonded to the floor of a recess formed within the housing, which capacitor forms a platform supporting the IC device. Leads between the capacitor and the power supply terminals of the circuit may be maintained at extremely short lengths, whereby inductances are minimized and relatively small capacitors effectively damp power supply pulses.