Abstract: A phase-change material is proposed for coupling interconnect lines an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer between the phase change material and at least one of the lines. The matrix array may be used in a programmable logic device. The logic portions of the programmable logic device may be tri-stated.

Abstract: An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh. In some embodiments, the circuitry may further include shift registers and one or more arithmetic logic units to provide a video memory.

Abstract: A phase change memory cells including a memory element or a threshold device is read using a read current which does not threshold either the memory element or the threshold device in the case of both a set and a reset memory element. As a result, higher currents may be avoided, increasing read endurance. A sensing circuit includes a charging rate detector coupled to a selected address line and sensing a rate of change of a voltage on the selected address line.

Abstract: A three-dimensional memory array formed of one or more two-dimensional memory arrays of one-time programmable memory elements arranged in horizontal layers and stacked vertically upon one another; and a two-dimensional memory array of reprogrammable phase change memory elements stacked on the one or more two-dimensional memory arrays as the top layer of the three-dimensional memory array.

Abstract: An array of non-volatiel memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh.

Abstract: A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the material. The threshold voltage may be changed with pulses of different amplitude and/or different pulse fall times. Reading may be done using a reference level between the threshold voltages of the two different states. A separate access device is generally not needed.

Abstract: A phase change memory may be made using an isolation diode in the form of a Schottky diode between a memory cell and a word line. The use of Schottky diode isolation devices may make the memory more scaleable in some embodiments.

Abstract: In accordance with some embodiments, the endurance of phase change memory cells may be increased. This increase may be accomplished with adequate margin by reducing the current used to write the reset state. Generally, that current will be a current less than the saturated current.

Abstract: A memory includes a storage element (OUM) made of a phase-change material for storing a logic value and an access element (OTS) switching from a higher resistance condition to a lower resistance condition in response to a selection of the memory cell, the access element in the higher resistance condition decoupling the storage element from a read circuit and in the lower resistance condition coupling the storage element to the read circuit. The read circuit includes a sense amplifier to determine the logic value stored in the memory cell according to an electrical quantity associated with the memory cell. The read circuit further includes a detector that detects the switching of the access element by comparison to a delayed waveform or sensing a change in the column rate of change, and a circuit to enable the sense amplifier in response to the detection of the switching of the access element.

Abstract: A static random access memory may be formed using a bitline and a bitline bar coupled to ovonic threshold switches. The ovonic threshold switches may, in turn, be coupled to cross coupled NMOS transistors. In some embodiments, a very compact static random access memory may result.

Abstract: A method of reading a phase-change memory element. The memory element is read by establishing a read voltage across the memory element. The read voltage is preferably greater than the holding voltage of the memory element.

Abstract: A phase change memory may be read so as to reduce the likelihood of a read disturb. A read disturb may occur, for example, when a reset device is raised to a voltage, which causes its threshold device to trigger. The triggering of the threshold device produces a displacement current which may convert a reset device to a set device. By ensuring that the reset cell never reaches a voltage that would result in triggering of the threshold device, read disturbs may be reduced.

Abstract: A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.

Abstract: A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some embodiments. A refresh cycle may be included at periodic intervals.

Abstract: A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some embodiments. A refresh cycle may be included at periodic intervals.

Abstract: A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.

Abstract: A memory includes a storage element (OUM) made of a phase-change material for storing a logic value and an access element (OTS) switching from a higher resistance condition to a lower resistance condition in response to a selection of the memory cell, the access element in the higher resistance condition decoupling the storage element from a read circuit and in the lower resistance condition coupling the storage element to the read circuit. The read circuit includes a sense amplifier to determine the logic value stored in the memory cell according to an electrical quantity associated with the memory cell. The read circuit further includes a detector that detects the switching of the access element by comparison to a delayed waveform or sensing a change in the column rate of change, and a circuit to enable the sense amplifier in response to the detection of the switching of the access element.

Abstract: A chalcongenide material is proposed for programming the cross-connect transistor coupling interconnect lines of an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer in series with the select device or a phase change material. The matrix array may be used in a programmable logic device.

Abstract: A memory element, a threshold switching element, or the series combination of a memory element and a threshold switching element may be used for coupling conductive lines in an electrically programmable matrix array. Leakage may be reduced by optionally placing a breakdown layer in series with the phase-change material and/or threshold switching material between the conductive lines. The matrix array may be used in a programmable logic device.

Abstract: A phase-change material is proposed for coupling interconnect lines an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer between the phase change material and at least one of the lines. The matrix array may be used in a programmable logic device. The logic portions of the programmable logic device may be tri-stated.