Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

Abstract: A semiconductor device including vertical transistors with a back side power structure, and methods of making the same are described. In one example, a described semiconductor structure includes: a gate structure including a gate pad and a gate contact on the gate pad; a first source region disposed below the gate pad; a first drain region disposed on the gate pad, wherein the first source region, the first drain region and the gate structure form a first transistor; a second source region disposed below the gate pad; a second drain region disposed on the gate pad, wherein the second source region, the second drain region and the gate structure form a second transistor; and at least one metal line that is below the first source region and the second source region, and is electrically connected to at least one power supply.

Abstract: A semiconductor device includes a gate structure on a substrate, a spacer around the gate structure, and a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

Abstract: Methods, systems, and devices for wireless communications are described. A wireless device (e.g., a base station) may transmit, to a user equipment (UE), an indication of a field type of a field between the UE and the wireless device. The indication of the field type may include one or more bits indicating the field type, a measure indicating a likelihood that the field type includes a first field type as compared to a second field type, an indication that the first type is the same as a second field type configured at the UE, or any combination thereof. The UE may select between a first set of beam weight vectors and a second set of beam weight vectors based on the field type. The UE may communicate, with the base station, a reference signal using a beam generated using a first beam weight vector from the selected set.

Abstract: Some implementations described herein provide a semiconductor device and methods of formation. The semiconductor device includes a gate-all-around transistor having one or more dielectric regions that include or more dielectric gases. The dielectric regions may include a first dielectric region between epitaxial regions (e.g., source/drain regions) and a first portion of a gate structure of the gate-all-around transistor. The dielectric regions may further include a second dielectric region between a contact structure of gate-all-around transistor and a second portion of the gate structure. By including the dielectric regions in the gate-all-around transistor, a parasitic capacitance associated with the gate-all-around transistor may be reduced relative to another gate-all-around transistor not including the dielectric regions.

Abstract: The present invention provides a high electron mobility transistor, which includes a substrate, a buffer layer, a gallium nitride layer, a two-dimensional material structure, a covering layer, a drain, a source and a gate. The buffer layer is located on the substrate. The gallium nitride layer is located on the buffer layer and forms a channel layer. The two-dimensional material structure is located on the channel layer. The covering layer partially covers the two-dimensional material structure. The drain and the source are arranged on the two-dimensional material structure, and the gate is arranged on the covering layer.

Abstract: A method of forming a semiconductor device includes the following operations. A substrate is provided with an electric component. A composite dielectric layer is formed on the substrate and covers the electric component. An opening is formed through the composite dielectric layer. A directional etching process is performed to widen an upper portion of the opening. A metal feature is formed in the opening.

Abstract: The invention discloses a semiconductor package antenna structure and its manufacturing method, wherein the semiconductor package antenna structure includes a first substrate, a semiconductor chip, and a second substrate. The first substrate has at least two stacked first redistribution layers, and each of the first redistribution layers has a first dielectric layer, a first patterned metal layer, and/or a first conductive pillar layer. The semiconductor chip is embedded in the first substrate and coupled to the first redistribution layers. The second substrate has a second redistribution layer, a second conductive pillar layer, and an air dielectric layer, wherein the second conductive pillar layer is protruded from the second redistribution layer. The second substrate is connected to the first substrate by a second conductive pillar layer, and the air dielectric layer is located between the second redistribution layer, the second conductive pillar layer, and the first substrate.

Abstract: Disclosed is a user equipment (UE) configured to perform beam failure recovery with uplink antenna panel selection. In some embodiments, the UE determines a first UE antenna panel corresponding to a candidate beam detection (CBD) reference signal (RS); reports to a gNB a beam failure recovery request (BFRQ), the BFRQ including UE antenna panel information for the first UE antenna panel; and after receiving from the gNB a response to the BFRQ, changes from a second UE antenna panel to the first UE antenna panel and corresponding configuration for uplink transmission.

Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.

Abstract: A method for forming a metal oxide semiconductor device includes performing a first atomic layer deposition cycle M times to form a first stacked channel layer and a second atomic layer deposition cycle N times to form a second stacked channel layer on the first stacked channel layer. M and N are positive integers. The first stacked channel layer and the second stacked channel layer have different metal compositions and collectively form the channel layer of the metal oxide semiconductor device.

Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.

Abstract: A method for intra prediction includes: determining occupancy information of a first number of neighboring nodes of a coded node; determining occupancy information of a second number of neighboring nodes of the coded node based on a position association between at least one neighboring node of the coded node and a child node of the coded node, where the first number is greater than the second number; determining an occupancy number corresponding to the second number of neighboring nodes based on the occupancy information of the second number of neighboring nodes; and determining an occupancy prediction result of the child node of the coded node based on the occupancy number. A decoder and a method for intra prediction performed by the decoder are also provided.

Abstract: The present disclosure provides a structure of an ultraviolet light sensing-enhanced photodiode. The main structure of the photodiode includes a silicon photodiode and an infrared conversion layer formed on a surface that receives an ultraviolet light of the of the silicon photodiode. When the ultraviolet light irradiates on the ultraviolet light sensing-enhanced photodiode through the infrared conversion layer, the infrared conversion layer converts the ultraviolet light into an infrared light. The first portion of the infrared light is propagated to the silicon photodiode and then converted to a photoelectric current. The second portion of the infrared light is absorbed by the infrared conversion layer. An infrared reflection layer is also provided for reflecting the third portion of the infrared light that is originally escaped from the infrared reflection layer, and the third portion of the infrared light can be reflected into the silicon photodiode.

Abstract: An antenna base and an antenna set. The antenna set includes a host and the antenna base. The host is fixed with a plurality of first connectors. The host is detachably assembled to the antenna base. The antenna base includes a body, a plurality of antennas and a plurality of second connectors. The antenna is installed at the body. The second connectors are electrically connected to the antennas. The assembling of the host and the body and the electrical and structural connection of the first connector and the second connector are completed in the same time.

Abstract: A method of manufacturing an optical detection element includes: a first process of forming an amorphous semiconductor layer on a support; a second process of forming a first metal layer on the semiconductor layer; a third process of carrying out a heat treatment so that the semiconductor layer is polycrystallized and the semiconductor layer and the first metal layer are interchanged with each other, thereby forming the first metal layer on the support and forming a polycrystalline photoelectric conversion layer on the first metal layer; and a fourth process of forming a second metal layer on the photoelectric conversion layer. In the fourth process, the second metal layer is formed so that a width of the second metal layer becomes a width with which surface plasmon resonance occurs due to incidence of light in a predetermined wavelength region.

Abstract: The present invention provides a photodiode structure, which includes a chip, an electrode group, an electrode protection layer and a metal alloy band-pass optical film. The electrode group is arranged on the chip, and the electrode group includes a positive electrode and a negative electrode; the electrode protection layer is arranged on the chip and covers the electrode group; the metal alloy band-pass optical film is arranged on the electrode protection layer and includes a plurality of layered structures, and the plurality of layered structures includes at least two metal alloy material layers.

Abstract: The present application provides a light emitting diode (LED) chip, a display panel thereof, and a manufacturing method thereof. The display panel includes a plurality of LED light emitting devices, a plurality of first electrodes and a plurality of second electrodes. The LED light emitting device includes a central support element and a conductive portion covering a surface of the semiconductor layer. The conductive portion is electrically connected to the first electrode, a side surface of the conductive portion away from semiconductor layer is a spherical surface. A conductive cross-section is disposed on the semiconductor layer and configure to cut the spherical surface. A third electrode is disposed on the conductive cross-section and is electrically connected to the second electrode.

Abstract: A motor controller having a pulse width modulation generating mechanism is provided. A triangular wave signal generator circuit generates a triangular wave signal. A comparator compares the triangular wave signal with an input control signal to determine a pulse width modulation signal. A signal detector circuit detects a duty cycle of each of a plurality of pulse waves of the pulse width modulation signal. A control converter circuit converts the duty cycle of each of the plurality of pulse waves of the pulse width modulation signal as an arithmetic value into a control value, according to a preset ratio. A driver circuit drives a motor to rotate according to the control value from the control converter circuit.

Abstract: A subharmonic switching power amplifier architecture includes a power amplifier core that includes at least one power amplifier that receives an input signal and is operable in a power back-off region. Characteristically, the at least one power amplifier is configured to be toggled at a carrier frequency (Fc) when the power level of the input signal is equal to or higher than a predetermined power level and at a subharmonic component of the carrier frequency when the power level of the input signal is less than the predetermined power level. Concurrent harmonic tuning and subharmonic tuning is implemented to enhance the efficiency at both peak power mode and power back-off mode. Characteristically, the power amplifier being configured to be operated by a voltage mode or current mode driver and in the current mode with zero-voltage-switching.