Patents by Inventor Wei Chan
Wei Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966085Abstract: An optical transceiver includes an input assembly, an output port, a fiber patch panel, multiple first optical fibers and multiple second optical fibers. The input assembly is arranged on a circuit board and has a first input port and a second input port. The fiber patch panel is arranged between the input assembly and the output port, and has multiple first fiber patch slots and multiple second fiber patch slots. The first optical fibers are connected to the first input port and the output port. The first optical fiber passes through the first fiber patch slot and the second fiber patch slot. The second optical fibers are connected to the second input port and the output port. The second optical fiber passes through the first fiber patch slot and the second fiber patch slot. The second fiber patch slot accommodates the first optical fiber and the second optical fiber.Type: GrantFiled: May 19, 2021Date of Patent: April 23, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Chen-Mao Lu, Wei-Chan Hsu, Chun-Yen Chen
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Patent number: 11968038Abstract: Disclosed are systems, methods, and non-transitory computer-readable storage media for monitoring application health via correctable errors. The method includes identifying, by a network device, a network packet associated with an application and detecting an error associated with the network packet. In response to detecting the error, the network device increments a counter associated with the application, determines an application score based at least in part on the counter, and telemeters the application score to a controller. The controller can generate a graphical interface based at least in part on the application score and a timestamp associated with the application score, wherein the graphical interface depicts a trend in correctable errors experienced by the application over a network.Type: GrantFiled: July 19, 2021Date of Patent: April 23, 2024Assignee: Cisco Technology, Inc.Inventors: Keerthi Manjunathan Swarnamanjunathan, Chih-Tsung Huang, Kelvin Chan, Wei-Jen Huang
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Patent number: 11964881Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.Type: GrantFiled: July 27, 2020Date of Patent: April 23, 2024Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
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Organometallic complex, catalyst composition employing the same, and method for preparing polyolefin
Patent number: 11958929Abstract: An organometallic complex, a catalyst composition employing the same, and a method for preparing polyolefin are provided. The organometallic compound has a structure represented by Formula (I) wherein M is Ti, Zr, or Hf; X is —O—, or —NR6—; R1 and R2 are independently hydrogen, C1-6 alkyl group, C6-12 aryl group, or R1 and R2 are combined with the carbon atoms, to which they are attached, to form an C6-12 aryl moiety; R3, R4 and R5 are independently fluoride, chloride, bromide, C1-6 alkyl group, C6-12 aryl group, C3-6 hetero aryl group, C7-13 aryl alkyl group or C7-12 alkyl aryl group; and R6 is hydrogen, C6-12 aryl group or C7-12 alkyl aryl group.Type: GrantFiled: June 24, 2022Date of Patent: April 16, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chien-Wei Hsu, Jyun-Wei Hong, Pao Tsern Lin, Shu-Hua Chan -
Patent number: 11951165Abstract: Methods for the production of immunogenic compositions containing a non-natural amino acid are disclosed. The non-natural amino acid can be a site for attachment of antigens, such as bacterial capsular polysaccharides, to make immunogenic conjugates. Bio-orthogonal attachment chemistry incorporated into the non-natural amino acids allows for more efficient and potent antigen presentation to the immune system, simplified purification, and more well-defined structure of these semi-synthetic immunogens.Type: GrantFiled: July 1, 2019Date of Patent: April 9, 2024Assignee: Vaxcyte, Inc.Inventors: Jeffery C. Fairman, Jon H. Heinrichs, Wei Chan
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Patent number: 11952915Abstract: A fan includes a hub and a plurality of fan blades. The hub has an axle center. The fan blades are disposed around the hub. Each of the fan blades has a bent portion, and the bent portions of the fan blades are extended along a surrounding direction surrounding the axle center. The hub is welded with the bent portion of each of the fan blades along the surrounding direction. As a result, the number of fan blades is maximized, the strength is simultaneously ensured to be enough, and the advantages of effectively enhancing the fan characteristics are achieved.Type: GrantFiled: June 13, 2023Date of Patent: April 9, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Ching-Hsien Yeh, Chih-Wei Chan
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Patent number: 11955507Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.Type: GrantFiled: September 9, 2021Date of Patent: April 9, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Hsin-Hung Li, Wei-Syun Wang, Chih-Chiang Chen, Yu-Cheng Shih, Cheng-Chan Wang, Chia-Hsin Chung, Ming-Jui Wang, Sheng-Ming Huang
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Patent number: 11953523Abstract: An analog front-end (AFE) circuit, configured to be coupled to a sensor having a plurality of sensing units, includes a plurality of sensing circuits and a plurality of multiplexers. Each of the plurality of multiplexers is coupled between one of the plurality of sensing units and at least two of the plurality of sensing circuits.Type: GrantFiled: November 30, 2021Date of Patent: April 9, 2024Assignee: NOVATEK Microelectronics Corp.Inventors: Tzu-Wei Lin, Hung-Kai Chen, Feng-Lin Chan
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Patent number: 11948837Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.Type: GrantFiled: August 30, 2021Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Fu Yeh, Chin-Lung Chung, Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee
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Patent number: 11946945Abstract: A sample analyzing method and a sample preparing method are provided. The sample analyzing method includes a sample preparing step, a placing step, and an analyzing step. The sample preparing step includes an obtaining step implemented by obtaining an identification information; and a marking and placing step implemented by placing a sample carrying component having a sample disposed thereon into a marking equipment, allowing the marking equipment to utilize the identification information to form an identification structure on the sample carrying component, and placing the sample carrying component into one of the accommodating slots according to the identification information. The placing step is implemented by taking out the sample carrying component from one of the accommodating slots and placing the sample carrying component into an electron microscope equipment. The analyzing step is implemented by utilizing the electron microscope equipment to photograph the sample to generate an analyzation image.Type: GrantFiled: July 29, 2021Date of Patent: April 2, 2024Assignee: MATERIALS ANALYSIS TECHNOLOGY INC.Inventors: Keng-Chieh Chu, Tsung-Ju Chan, Chun-Wei Wu, Hung-Jen Chen
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Publication number: 20240102799Abstract: An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.Type: ApplicationFiled: December 5, 2023Publication date: March 28, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ying-Chung CHEN, Hsun-Wei CHAN, Lu-Ming LAI, Kuang-Hsiung CHEN
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Patent number: 11935878Abstract: A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.Type: GrantFiled: September 10, 2021Date of Patent: March 19, 2024Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Hsiu-Mei Yu, Guang-Yuan Jiang, Cheng-Yi Hsieh, Wei-Chan Chang, Chang-Sheng Lin
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Publication number: 20240088042Abstract: A semiconductor structure includes a dielectric layer over a substrate, a via conductor over the substrate and in the dielectric layer, and a first graphene layer disposed over the via conductor. In some embodiments, a top surface of the via conductor and a top surface of the dielectric layer are level. In some embodiments, the first graphene layer overlaps the via conductor from a top view. In some embodiments, the semiconductor structure further includes a second graphene layer under the via conductor and a third graphene layer between the dielectric layer and the via conductor. In some embodiments, the second graphene layer is between the substrate and the via conductor.Type: ApplicationFiled: January 11, 2023Publication date: March 14, 2024Inventors: SHU-WEI LI, HAN-TANG HUNG, YU-CHEN CHAN, CHIEN-HSIN HO, SHIN-YI YANG, MING-HAN LEE, SHAU-LIN SHUE
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Publication number: 20240086090Abstract: An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.Type: ApplicationFiled: September 14, 2022Publication date: March 14, 2024Inventors: Yang Lu, Yu-Sheng Hsu, Kang-Yong Kim, Ke Wei Chan
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Publication number: 20240082817Abstract: The invention concerns biocompatible polymer systems comprising at least one polymer with a plurality of pores, said polymer comprising either polyol or zwitterionic groups designed to adsorb endotoxins and other inflammatory mediator molecules.Type: ApplicationFiled: November 6, 2023Publication date: March 14, 2024Inventors: Tamaz Guliashvili, Thomas Golobish, Maryann Gruda, Pamela O'Sullivan, Andrew Scheirer, Vincent Capponi, Phillip Chan, Wei-Tai Young
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Patent number: 11923295Abstract: A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a second dielectric layer on the high resistance layer, a low-k dielectric layer over the second dielectric layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer.Type: GrantFiled: June 19, 2020Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hong-Wei Chan, Yung-Shih Cheng, Wen-Sheh Huang, Yu-Hsiang Chen
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Patent number: 11923205Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.Type: GrantFiled: December 17, 2021Date of Patent: March 5, 2024Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Kun-Ju Li, Ang Chan, Hsin-Jung Liu, Wei-Xin Gao, Jhih-Yuan Chen, Chun-Han Chen, Zong-Sian Wu, Chau-Chung Hou, I-Ming Lai, Fu-Shou Tsai
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Patent number: 11924705Abstract: An antenna device, a positioning system and a positioning method are provided. The positioning method includes: dispersedly arranging a plurality of receivers to form a target area, in which each of the receivers includes the antenna device; receiving a wireless signal from the target area through the antenna device, and generating a difference signal strength and a sum signal strength; calculating, for each of the receivers, a sum-difference ratio between the difference signal strength and the sum signal strength, and estimating a corresponding one of estimated incident angles according to the sum-difference ratio and a comparison table; executing, in response to obtaining the estimated incident angles corresponding to the receivers, a positioning algorithm according to the estimated incident angles, so as to generate a plurality of possible positions; and executing an optimization algorithm to calculate a best estimated position of the possible positions.Type: GrantFiled: January 20, 2022Date of Patent: March 5, 2024Assignee: PSJ INTERNATIONAL LTD.Inventors: Shih-Yi Huang, Hao-Wei Chan, Ruey-Beei Wu
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Publication number: 20240071988Abstract: A method for manufacturing a semiconductor structure is provided. The method includes: providing a substrate and a dielectric layer on the substrate; forming a hole in the dielectric layer; forming an initial barrier material layer and a conductive layer on an upper surface of the dielectric layer and in the hole; removing part of the initial barrier material layer and part of the conductive layer to form a barrier material layer and a via element in the hole respectively and expose the upper surface of the dielectric layer. An upper surface of the barrier material layer is higher than the upper surface of the dielectric layer.Type: ApplicationFiled: October 11, 2022Publication date: February 29, 2024Inventors: Kun-Ju LI, Hsin-Jung LIU, Wei-Xin GAO, Jhih-Yuan CHEN, Ang CHAN, Chau-Chung HOU
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Patent number: D1019023Type: GrantFiled: March 30, 2020Date of Patent: March 19, 2024Assignee: Amazon Technologies, Inc.Inventors: Michael Edward James Paterson, Chia-Wei Chan, Mei Hsuan Chen, Benjamin Wild, Matthew J. England, Wen-Yo Lu, James Siminoff, Mark Siminoff, Yen-Chi Tsai