Patents by Inventor Wei Chan

Wei Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11776862
    Abstract: The present disclosure relates to a semiconductor device package, which includes a carrier, a lid, a first adhesive layer and a constraint structure. The carrier includes a surface and a first conductive pad on the surface of the carrier. The lid includes a first portion and a second portion separated from the first portion on the surface of the carrier. The first conductive pad is disposed between the first portion of the lid and the surface of the carrier. The first adhesive layer includes a first portion between the first portion of the lid and the first conductive pad. The constraint structure surrounds the first adhesive layer.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: October 3, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Han Chen, Hsun-Wei Chan, Mei-Yi Wu
  • Publication number: 20230298244
    Abstract: In some implementations, the disclosed systems and methods can create a customized pet avatar by applying artificial intelligence to photographs and videos of a real-world pet. In some implementations, the disclosed systems and methods can geospatially map user-generated content within a VR environment. In some implementations, the disclosed systems and methods can receive user-generated content (e.g., images, videos, text, etc.) about a particular destination, such as a business listing, restaurant, or other location of interest. In some implementations, the disclosed systems and methods can build a selected virtual object of a plurality of virtual objects in an artificial reality world.
    Type: Application
    Filed: April 21, 2023
    Publication date: September 21, 2023
    Applicant: Meta Platforms Technologies, LLC
    Inventors: Chun-Wei CHAN, Meng WANG, Maria Alejandra RUIZ GUTIERREZ, Michelle Jia-Ying CHEUNG, Jiemin ZHANG, Vincent Charles CHEUNG
  • Patent number: 11762706
    Abstract: Methods, systems, and computer-readable media that manage cloud computing environments. A pool manager creates a pool of cloud computing environments according to a pool specification specifying a headroom threshold of the pool. The pool manager receives, from a requester computer, a request to claim a cloud computing environment. The pool manager determines that one or more cloud computing environments are available. In response, the pool manager provides to the requesting computer credentials for accessing the cloud computing environment. The pool manager designates the cloud computing environment as claimed and unavailable to other requester computers until receiving a notification indicating that the cloud computing environment is unclaimed. The pool manager ensures that the correct number of environments are available on a pre-determined schedule.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: September 19, 2023
    Assignee: VMware, Inc.
    Inventors: Michael Jarvis, Mark Stokan, Kenneth Lakin, Der Wei Chan, Navdeep Pama
  • Publication number: 20230289234
    Abstract: Methods, systems, and computer-readable media that manage cloud computing environments. A pool manager creates a pool of cloud computing environments according to a pool specification specifying a headroom threshold of the pool. The pool manager receives, from a requester computer, a request to claim a cloud computing environment. The pool manager determines that one or more cloud computing environments are available. In response, the pool manager provides to the requesting computer credentials for accessing the cloud computing environment. The pool manager designates the cloud computing environment as claimed and unavailable to other requester computers until receiving a notification indicating that the cloud computing environment is unclaimed. The pool manager ensures that the correct number of environments are available on a pre-determined schedule.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 14, 2023
    Inventors: Michael Jarvis, Mark Stokan, Kenneth Lakin, Der Wei Chan, Navdeep Pama
  • Patent number: 11756924
    Abstract: A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hong-Wei Chan, Jiing-Feng Yang, Yung-Shih Cheng, Yao-Te Huang, Hui Lee
  • Fan
    Patent number: 11719106
    Abstract: A fan includes a hub and a plurality of fan blades. The hub has an axle center. The fan blades are disposed around the hub. Each of the fan blades has a bent portion, and the bent portions of the fan blades are extended along a surrounding direction surrounding the axle center. The hub is welded with the bent portion of each of the fan blades along the surrounding direction. As a result, the number of fan blades is maximized, the strength is simultaneously ensured to be enough, and the advantages of effectively enhancing the fan characteristics are achieved.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: August 8, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Ching-Hsien Yeh, Chih-Wei Chan
  • Publication number: 20230246142
    Abstract: A package structure includes a circuit substrate, a light emitting diode array, a first encapsulant, and a sealant. The circuit substrate includes a top surface and a side surface of the circuit substrate. The light emitting diode array is disposed on the top surface of the circuit substrate. The first encapsulant is disposed above the circuit substrate. The first encapsulant includes a main portion and an extension portion, in which the main portion of the first encapsulant is disposed parallel to the top surface of the circuit substrate, and the extension portion of the first encapsulant extends to the side surface of the circuit substrate. The sealant is disposed below the extension portion of the first encapsulant, and the sealant contacts the first encapsulant and the circuit substrate. The first encapsulant and the sealant together form a coplanar surface.
    Type: Application
    Filed: December 7, 2022
    Publication date: August 3, 2023
    Inventors: Fu-Wei CHAN, Kuan-Hsun CHEN, Yi-Hsin LIN
  • Publication number: 20230238308
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a lead frame and a sub-substrate disposed on the lead frame, wherein the thickness of the sub-substrate is between 0 and 0.5 ?m. The semiconductor structure also includes an epitaxial layer disposed on the sub-substrate. The epitaxial layer includes a buffer layer, a channel layer and a barrier layer. The buffer layer is disposed between the sub-substrate and the channel layer. The channel layer is disposed between the buffer layer and the barrier layer. The semiconductor structure further includes a device layer disposed on the barrier layer and an interconnector structure electrically connected to the epitaxial layer and/or the device layer by a through hole.
    Type: Application
    Filed: January 27, 2022
    Publication date: July 27, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsiu-Mei YU, Guang-Yuan JIANG, Cheng-Yi HSIEH, Wei-Chan CHANG, Chang-Sheng LIN
  • Publication number: 20230187417
    Abstract: A display panel includes a substrate, light-emitting diodes, and a cured opaque encapsulant layer. The light-emitting diodes are disposed on a first surface of the substrate. The cured opaque encapsulant layer is disposed on the first surface and a side surface of the substrate, and surrounds the light emitting diodes. A second surface of the cured opaque encapsulant layer facing away from the substrate is a rough surface.
    Type: Application
    Filed: April 1, 2022
    Publication date: June 15, 2023
    Applicant: Au Optronics Corporation
    Inventors: Fu-Wei Chan, Kuan-Hsun Chen, Yi-Yueh Hsu
  • Publication number: 20230144893
    Abstract: Methods and systems described herein are directed to creating an artificial reality environment having elements automatically created from source images. In response to a creation system receiving the source images, the system can employ a multi-layered comparative analysis to obtain virtual object representations of objects depicted in the source images. A first set of the virtual objects can be selected from a library by matching identifiers for the depicted objects with tags on virtual objects in the library. A second set of virtual objects can be objects for which no candidate first virtual objects was adequately matched in the library, prompting the creation of a virtual object by generating depth data and skinning a resulting 3D mesh based on the source images. Having determined the virtual objects, the system can compile them into the artificial reality environment according to relative locations determined from the source images.
    Type: Application
    Filed: March 8, 2022
    Publication date: May 11, 2023
    Inventor: Chun-Wei CHAN
  • Publication number: 20230129169
    Abstract: An apparatus for treating gaseous pollutants includes a gas inlet part, a first treatment unit, a second treatment unit and a non-mechanical flow-guiding device. The gas inlet part includes a gas inlet chamber and at least one guide pipe. The guide pipe communicates with the gas inlet chamber and guides an effluent stream from a semiconductor process to the gas inlet chamber. The first treatment unit is coupled to a bottom end of the gas inlet part and is configured to abate the effluent stream. The non-mechanical flow-guiding device is coupled to the first treatment unit. The flow-guiding device is configured to guide the effluent stream to move toward an opening. The second treatment unit is coupled to the flow-guiding device via the opening, receives the effluent stream from the first treatment unit and further abates the effluent stream.
    Type: Application
    Filed: December 22, 2022
    Publication date: April 27, 2023
    Inventor: Chee Wei CHAN
  • Publication number: 20230124926
    Abstract: An apparatus for treating gaseous pollutants includes a gas inlet part, a first treatment unit, a second treatment unit and a non-mechanical flow-guiding device. The gas inlet part includes a gas inlet chamber and at least one guide pipe. The guide pipe communicates with the gas inlet chamber and guides an effluent stream from a semiconductor process to the gas inlet chamber. The first treatment unit is coupled to a bottom end of the gas inlet part and is configured to abate the effluent stream. The non-mechanical flow-guiding device is coupled to the first treatment unit. The flow-guiding device is configured to guide the effluent stream to move toward an opening. The second treatment unit is coupled to the flow-guiding device via the opening, receives the effluent stream from the first treatment unit and further abates the effluent stream.
    Type: Application
    Filed: December 20, 2022
    Publication date: April 20, 2023
    Inventor: Chee Wei CHAN
  • Publication number: 20230117093
    Abstract: An apparatus for treating gaseous pollutants includes a gas inlet part, a first treatment unit, a second treatment unit and a non-mechanical flow-guiding device. The gas inlet part includes a gas inlet chamber and at least one guide pipe. The guide pipe communicates with the gas inlet chamber and guides an effluent stream from a semiconductor process to the gas inlet chamber. The first treatment unit is coupled to a bottom end of the gas inlet part and is configured to abate the effluent stream. The non-mechanical flow-guiding device is coupled to the first treatment unit. The flow-guiding device is configured to guide the effluent stream to move toward an opening. The second treatment unit is coupled to the flow-guiding device via the opening, receives the effluent stream from the first treatment unit and further abates the effluent stream.
    Type: Application
    Filed: December 20, 2022
    Publication date: April 20, 2023
    Inventor: Chee Wei CHAN
  • Publication number: 20230114585
    Abstract: A ranging-type positioning system and a ranging-type positioning method based on crowdsourced calibration are provided. In a crowdsourcing stage, pedestrian dead reckoning (PDR) is performed based on readings of inertial measurement units on a mobile device, a particle filter (PF) is executed to reconstruct a path of the mobile device with map information of the target field, and FTM data records are collected. Then, a ranging model based on a neural network can be used to calibrate and inversely infer approximate locations of unknown base stations. The optimized ranging model can estimate estimated distances and standard deviations based on the FTM data records obtained in the crowdsourcing stage. In a positioning stage, a position of a to-be-positioned mobile device can be positioned by having the ranging model operated in cooperation with the PDR and the PF.
    Type: Application
    Filed: May 26, 2022
    Publication date: April 13, 2023
    Inventors: HAO-WEI CHAN, ALEXANDER I CHI LAI, Ruey-Beei Wu
  • Publication number: 20230099825
    Abstract: A power supply device is provided with a secure power supply device, a voltage detection circuit, a stable voltage source and a switch. By using the voltage detection circuit, whether a driving voltage of an encryption/decryption device is insufficient to control the on and off the switch, so as to determine whether only the secure power supply device provides a supply voltage to the encryption/decryption device as the driving voltage. Alternatively, the supply voltage of the secure power supply device and a stable voltage of the stable voltage source are provided simultaneously to the encryption/decryption device as the driving voltage. In other words, once the driving voltage drops (that is, the encryption/decryption device consumes a large current for encryption/decryption), the stable voltage source immediately provides the stable voltage to the encryption/decryption device as part of the driving voltage to ensure that the encryption/decryption device can normally work.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 30, 2023
    Inventors: WEI-CHAN HSU, PO-HSUAN HUANG, CHUNG MING HSIEH
  • Publication number: 20230093736
    Abstract: A centrifugal fan is disclosed and includes a housing, a fan wheel, a first throat portion and a second throat portion. The housing includes a lower cover connected to an upper cover through a peripheral wall to form an accommodation space and an outlet. The upper cover includes an inlet communicated with the outlet. The fan wheel is disposed on the lower cover and accommodated in the accommodation space. The fan wheel is rotated along a rotation direction. The first throat portion is disposed adjacent to a lateral end of the outlet and protrudes from the peripheral wall toward the accommodation space. The second throat portion is disposed adjacent to another lateral end of the outlet, and protrudes from the peripheral wall toward the accommodation space. When the fan wheel is rotated along the rotational direction, an airflow is guided from the first throat portion to the second throat portion.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 23, 2023
    Inventors: Chin-Hung Lee, Chih-Wei Chan, Ya-Ting Chang
  • Publication number: 20230083337
    Abstract: A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 16, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsiu-Mei YU, Guang-Yuan JIANG, Cheng-Yi HSIEH, Wei-Chan CHANG, Chang-Sheng LIN
  • Publication number: 20230077278
    Abstract: Some aspects of the disclosed technology can create a virtual object based on user container selections. Further aspects of the disclosed technology can provide one or more product recommendations corresponding to a current context of user activity. Additional aspects of the disclosed technology can generate and export non-fungible tokens using object recognition. Yet further aspects of the disclosed technology can augment a digital environment with NFT content corresponding to an NFT wallet.
    Type: Application
    Filed: November 14, 2022
    Publication date: March 9, 2023
    Applicant: Meta Platforms Technologies, LLC
    Inventors: Miguel GONCALVES, Hsin-Yao LIN, Patrick BENJAMIN, Yiting LI, Chun-Wei CHAN, Yinglong XIA, Jiajie TANG, Jeffrey Thomas CLARKE, Erik Christopher LARSSON, Rachel CIAVARELLA, Marco Andre LOURENÇO DE SOUSA
  • Patent number: 11601050
    Abstract: A voltage regulation system is provided. In the voltage regulation system, a frequency of a clock signal is adjusted and a pulse generator is controlled to output a pulse signal to a switch power stage circuit, to enable the switch power stage circuit to adjust an output voltage and output the adjusted output voltage to the load element. Through the aforementioned configuration, the switch power stage circuit adjusts the output voltage according to the situation of the load element, thus decreasing the power loss of the switch power stage circuit.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 7, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Chung-Ming Hsieh, Wei-Chan Hsu
  • Patent number: 11588036
    Abstract: A chip structure includes a substrate, a bottom conductive layer, a semiconductor layer, an interlayer dielectric layer, at least one electrode, and at least one top electrode. The substrate includes in order a core layer and a composite material. The bottom conductive layer is disposed on the bottom surface of the core layer, the semiconductor layer is disposed on the substrate, and an interlayer dielectric layer is disposed on the semiconductor layer. The at least one electrode is disposed between the semiconductor layer and the interlayer dielectric layer, and the at least one top electrode is disposed on the interlayer dielectric layer and electrically coupled to the at least one electrode.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: February 21, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsiu-Mei Yu, Cheng-Yi Hsieh, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu