Patents by Inventor Wei Chan

Wei Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11588081
    Abstract: A semiconductor device package includes a light-emitting device, a diffuser structure, a first optical sensor, and a second optical sensor. The light-emitting device has a light-emitting surface. The diffuser structure is above the light-emitting surface of the light-emitting device. The first optical sensor is disposed below the diffuser structure, and the first optical sensor is configured to detect a first reflected light reflected by the diffuser structure. The second optical sensor is disposed below the diffuser structure, and the second optical sensor is configured to detect a second reflected light reflected by the diffuser structure.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: February 21, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsin-Ying Ho, Hsun-Wei Chan, Shih-Chieh Tang, Lu-Ming Lai
  • Publication number: 20230044484
    Abstract: An antenna device, a positioning system and a positioning method are provided. The positioning method includes: dispersedly arranging a plurality of receivers to form a target area, in which each of the receivers includes the antenna device; receiving a wireless signal from the target area through the antenna device, and generating a difference signal strength and a sum signal strength; calculating, for each of the receivers, a sum-difference ratio between the difference signal strength and the sum signal strength, and estimating a corresponding one of estimated incident angles according to the sum-difference ratio and a comparison table; executing, in response to obtaining the estimated incident angles corresponding to the receivers, a positioning algorithm according to the estimated incident angles, so as to generate a plurality of possible positions; and executing an optimization algorithm to calculate a best estimated position of the possible positions.
    Type: Application
    Filed: January 20, 2022
    Publication date: February 9, 2023
    Inventors: Shih-Yi Huang, Hao-Wei Chan, Ruey-Beei Wu
  • Publication number: 20230003380
    Abstract: An apparatus for treating gaseous pollutant with plasma comprises a microwave source generating a microwave oscillation; a waveguide component coupled to the microwave source; and a resonant cavity coupled to the waveguide component, the microwave oscillation is substantially propagated toward a waveguide direction, the resonant cavity comprises a first chamber and a second chamber, the waveguide direction is substantially parallel to a reference axis defined in the first chamber, the first chamber has an inner wall surrounding the reference axis, the inner wall comprises a first inner wall obliquely inclined toward the reference axis and a second inner wall substantially parallel in respect to the reference axis relatively, an area of the first inner wall is larger than that of the second inner wall so that the first chamber has a tapered space, and the microwave oscillation interacts with an ignition gas in the second chamber to generate a torch.
    Type: Application
    Filed: November 7, 2019
    Publication date: January 5, 2023
    Inventor: Chee Wei CHAN
  • Publication number: 20220416111
    Abstract: An optical device includes a substrate, an electronic component and a lid. The electronic component is disposed on the substrate. The lid is disposed on the substrate. The lid has a first cavity over the electronic component and a second cavity over the first cavity. The sidewall of the second cavity is inclined.
    Type: Application
    Filed: August 30, 2022
    Publication date: December 29, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang Chin TSAI, Yu-Che HUANG, Hsun-Wei CHAN
  • Publication number: 20220383070
    Abstract: Embodiments described herein provide methods and systems for generating data samples with enhanced attribute values. Some embodiments of the disclosure disclose a deep neural network framework with an encoder, a decoder, and a latent space therebetween, that is configured to extrapolate beyond the attributes of samples in a training distribution to generate data samples with enhanced attribute values by learning the latent space using a combination of contrastive objective, smoothing objective, cycle consistency objective, and a reconstruction loss.
    Type: Application
    Filed: June 21, 2021
    Publication date: December 1, 2022
    Inventors: Ali Madani, Alvin Guo Wei Chan
  • FAN
    Publication number: 20220372883
    Abstract: A fan includes a hub and a plurality of fan blades. The hub has an axle center. The fan blades are disposed around the hub. Each of the fan blades has a bent portion, and the bent portions of the fan blades are extended along a surrounding direction surrounding the axle center. The hub is welded with the bent portion of each of the fan blades along the surrounding direction. As a result, the number of fan blades is maximized, the strength is simultaneously ensured to be enough, and the advantages of effectively enhancing the fan characteristics are achieved.
    Type: Application
    Filed: August 4, 2022
    Publication date: November 24, 2022
    Inventors: Ching-Hsien Yeh, Chih-Wei Chan
  • Patent number: 11506849
    Abstract: The disclosure relates to an optical transceiver and a manufacturing method thereof. The optical transceiver includes a substrate, a thermal-conductive substrate, a first metal wiring structure, a light-transceiving element and an optical fiber array. The substrate has an opening, and the thermal-conductive substrate is embedded within the opening. The first metal wiring structure is integrally formed on the substrate and the thermal-conductive substrate through an electroplating or a wire-printing process. The light-transceiving element is disposed on the thermal-conductive substrate and is electrically connected to the first metal wiring structure. The optical fiber array is arranged on the thermal-conductive substrate for communication with the light-transceiving element.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: November 22, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Kuang-Yao Chen, Kao-Chi Chen, Wei-Chan Hsu, Gow-Zin Yiu
  • Publication number: 20220359387
    Abstract: A method of forming a semiconductor device includes forming a conductive feature and a first punch stop layer, where the conductive feature has a first top surface, and where the first punch stop layer has a second top surface that is substantially level with the first top surface. The method further includes forming a resistive element over the first punch stop layer. The method further includes etching through a first portion of the resistive element to form a first trench that exposes both the second top surface of the first punch stop layer and a first sidewall surface of the resistive element. The method further includes forming a first conductive via within the first trench, where the first conductive via contacts the first sidewall surface of the resistive element.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Hong-Wei CHAN, Yung-Shih CHENG, Wen-Sheh HUANG
  • Publication number: 20220336583
    Abstract: A method includes forming a transistor over a front side of a substrate; forming a front-side interconnect structure over the transistor, the front-side interconnect structure comprising layers of conductive lines, and conductive vias interconnecting the layers of conductive lines; forming a first bonding layer over the front-side interconnect structure; forming a second bonding layer over a carrier substrate; bonding the front-side interconnect structure to the carrier substrate by pressing the first bonding layer against the second bonding layer; and forming a backside interconnect structure over a backside of the substrate after bonding the front-side interconnect structure to the carrier substrate.
    Type: Application
    Filed: September 20, 2021
    Publication date: October 20, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guan-Yao TU, Su-Jen SUNG, Tze-Liang LEE, Hong-Wei CHAN
  • Publication number: 20220321001
    Abstract: A power converter is provided. The power converter includes a switched-capacitor conversion circuit and an inductor buck circuit. The switched-capacitor conversion circuit receives an input voltage at an input terminal and performs a switching operation to convert the input voltage to an intermediate voltage. The inductor buck circuit is coupled to an output terminal of the switched-capacitor conversion circuit to receive the intermediate voltage and operates at a constant on-time to generate an output voltage at a conversion output terminal according to the intermediate voltage. The inductor buck circuit includes an inductor. In response to that a state of an inductor current used for charging the inductor corresponds to a predetermined condition, a switching action of the switching operation is enabled, so that the switched-capacitor conversion circuit is switched from a first turned-on state to a second turned-on state.
    Type: Application
    Filed: December 16, 2021
    Publication date: October 6, 2022
    Inventors: Po-Hsun HUANG, Wei-Chan HSU
  • Publication number: 20220310559
    Abstract: A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hong-Wei Chan, Jiing-Feng Yang, Yung-Shih Cheng, Yao-Te Huang, Hui Lee
  • Publication number: 20220310556
    Abstract: In an embodiment, a method includes performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure; performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition; planarizing the first bonding layer; forming a second bonding layer over a second substrate; pressing the second bonding layer onto the first bonding layer; and removing the first substrate.
    Type: Application
    Filed: June 17, 2021
    Publication date: September 29, 2022
    Inventors: Yao-Te Huang, Hong-Wei Chan, Yung-Shih Cheng
  • Publication number: 20220310527
    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming an interconnect structure over a device wafer. The device wafer includes a first integrated circuit, a semiconductor substrate, and a redistribution structure. The method further includes forming a metallization layer and a group of dummy insertion structures having a stepped pattern density in a topmost dielectric layer of the interconnect structure. The group of dummy insertion structures and the metallization layer are planarized with the dielectric layer. The method further includes forming a first bonding layer over the group of dummy insertion structures, the metallization layer, and the dielectric layer. The method further includes bonding a carrier wafer to the first bonding layer, forming an opening through the semiconductor substrate, and forming a conductive via in the opening and electrically coupled to the redistribution structure.
    Type: Application
    Filed: July 30, 2021
    Publication date: September 29, 2022
    Inventors: Yao-Te Huang, Hong-Wei Chan, Yung-Shih Cheng, Jiing-Feng Yang, Hui Lee
  • Fan
    Patent number: 11441433
    Abstract: A fan includes a hub and a plurality of fan blades. The hub has an axle center. The fan blades are disposed around the hub. Each of the fan blades has a bent portion, and the bent portions of the fan blades are extended along a surrounding direction surrounding the axle center. The hub is welded with the bent portion of each of the fan blades along the surrounding direction. As a result, the number of fan blades is maximized, the strength is simultaneously ensured to be enough, and the advantages of effectively enhancing the fan characteristics are achieved.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: September 13, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Ching-Hsien Yeh, Chih-Wei Chan
  • Patent number: 11437313
    Abstract: A method of forming a semiconductor device includes forming a conductive feature and a first punch stop layer, where the conductive feature has a first top surface, and where the first punch stop layer has a second top surface that is substantially level with the first top surface. The method further includes forming a resistive element over the first punch stop layer. The method further includes etching through a first portion of the resistive element to form a first trench that exposes both the second top surface of the first punch stop layer and a first sidewall surface of the resistive element. The method further includes forming a first conductive via within the first trench, where the first conductive via contacts the first sidewall surface of the resistive element.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Wei Chan, Yung-Shih Cheng, Wen-Sheh Huang
  • Patent number: 11430906
    Abstract: An optical device includes a substrate, an electronic component and a lid. The electronic component is disposed on the substrate. The lid is disposed on the substrate. The lid has a first cavity over the electronic component and a second cavity over the first cavity. The sidewall of the second cavity is inclined.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: August 30, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang Chin Tsai, Yu-Che Huang, Hsun-Wei Chan
  • Publication number: 20220252801
    Abstract: The disclosure relates to an optical transceiver and a manufacturing method thereof. The optical transceiver includes a substrate, a thermal-conductive substrate, a first metal wiring structure, a light-transceiving element and an optical fiber array. The substrate has an opening, and the thermal-conductive substrate is embedded within the opening. The first metal wiring structure is integrally formed on the substrate and the thermal-conductive substrate through an electroplating or a wire-printing process. The light-transceiving element is disposed on the thermal-conductive substrate and is electrically connected to the first metal wiring structure. The optical fiber array is arranged on the thermal-conductive substrate for communication with the light-transceiving element.
    Type: Application
    Filed: June 16, 2021
    Publication date: August 11, 2022
    Inventors: Kuang-Yao Chen, Kao-Chi Chen, Wei-Chan Hsu, Gow-Zin Yiu
  • Patent number: 11406934
    Abstract: The invention provides a device and system for decomposing and oxidizing of gaseous pollutants. A novel reaction portion reduces particle formation in fluids during treatment, thereby improving the defect of particle accumulation in a reaction portion. Also, the system includes the device, wherein a modular design enables the system to have the advantage of easy repair and maintenance.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: August 9, 2022
    Assignee: SIW ENGINEERING PTE. LTD.
    Inventor: Chee-Wei Chan
  • Patent number: D957125
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: July 12, 2022
    Assignee: Monos Travel Ltd.
    Inventors: Hubert Jan-Wei Chan, Seung Woo Shin, Victor King Ming Tam
  • Patent number: D970508
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 22, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Wen-Yo Lu, Christopher Loew, Matthew J. England, Chia-Wei Chan, Mark D. Siminoff