Abstract: The present disclosure provides a display device and a display method thereof. The display device includes a microlens array including a plurality of microlenses; and a display panel including a plurality of pixel islands, wherein the plurality of pixel islands are arranged in one-to-one correspondence with the plurality of microlenses, each pixel island includes a plurality of sub-pixels, light emitted by the plurality of sub-pixels of each pixel island enters a human eye through a microlens corresponding to the each pixel island and forms an image in the human eye, and regions where images formed by at least two pixel islands in the plurality of pixel islands via microlenses corresponding to the at least two pixel islands are located are connected.

Abstract: A transient voltage suppression device includes at least one P-type lightly-doped structure and at least one electrostatic discharge structure. The electrostatic discharge structure includes an N-type lightly-doped well, an N-type well, a first P-type heavily-doped area, and a first N-type heavily-doped area. The N-type lightly-doped well is formed in the P-type lightly-doped structure. The N-type well is formed in the N-type lightly-doped well. The doping concentration of the N-type lightly-doped well is less than that of the N-type well. The first P-type heavily-doped area is formed in the N-type well. The first N-type heavily-doped area is formed in the P-type lightly-doped structure.

Abstract: A tunable external cavity laser with dual gain chips, including: a polarization beam splitter having a beam splitting surface arranged at an angle of 45° with respect to a first direction and a second direction perpendicular to the first direction; a first gain chip arranged in the first direction; a second gain chip arranged in the second direction; a feedback cavity arranged in the first direction, wherein the feedback cavity and the first gain chip are respectively arranged on two opposite sides of the polarization beam splitter, and the feedback cavity includes at least one independent Fabry-Perot etalon, at least one air gap Fabry-Perot cavity and a mirror that are arranged in the first direction. The polarization beam splitter and the two gain chips cooperate to share the feedback cavity, so that a wavelength and a phase may be adjusted, and a larger tuning range may be obtained.

Abstract: A 3DIC structure includes a die, a conductive terminal, and a dielectric structure. The die is bonded to a carrier through a bonding film. The conductive terminal is disposed over and electrically connected to the die. The dielectric structure comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed laterally aside the die. The second dielectric layer is disposed between the first dielectric layer and the bonding film, and between the die and the boding film. A second edge of the second dielectric layer is more flat than a first edge of the first dielectric layer.

Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.

Abstract: A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.

Abstract: Method and apparatus for affine CPMV or ALF refinement are mentioned. According to this method, statistical data associated with the affine CPMV or ALF refinement are collected over a picture area. Updated parameters for the affine CPMV refinement or the ALF refinement are then derived based on the statistical data, where a process to derive the updated parameters includes performing multiplication using a reduced-precision multiplier for the statistical data. The reduced-precision multiplier truncates at least one bit of the mantissa part. In another embodiment, the process to derive the updated parameters includes performing reciprocal for the statistical data using a lookup table with (m?k)-bit input by truncating k bits from the m-bit mantissa part, and contents of the lookup table includes m-bit outputs. m and k are positive integers.

Abstract: A method for allocating perishable products based on machine learning, includes using a sales estimation model to evaluate estimated sales of a plurality of perishable products in a predetermined period, using a rating model to calculate a predetermined rate of the plurality of perishable products in the predetermined period according to the estimated sales, using an allocation model to adjust an allocation ratio of the plurality of perishable products in a plurality of marketing channels according to the estimated sales and the predetermined rate if a current rate is lower than the predetermined rate, and determining the numbers of perishable products allocated to the plurality of marketing channels according to the allocation ratio.

Abstract: An electronic package is provided, in which electronic elements and at least one packaging module including a semiconductor chip and a shielding structure covering the semiconductor chip are disposed on a carrier structure, an encapsulation layer encapsulates the electronic elements and the packaging module, and a shielding layer is formed on the encapsulation layer and in contact with the shielding structure. Therefore, the packaging module includes the semiconductor chip and the shielding structure and has a chip function and a shielding wall function simultaneously.

Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.

Abstract: A distributed battery management system, for managing a plurality of battery management units, wherein each of the battery management units, includes: a first battery cell, forming a charge-discharge connection at least with a second battery cell in a second battery management unit; a monitor circuit, monitoring a discharge process of the first battery cell via the charge-discharge connection, to record a discharge voltage time history of the first battery cell; and a calculation unit, calculating a real-time maximal energy storage capacity of the first battery cell, by an electrochemical equation calculated based on the discharge voltage time history and an electrical current time history of the first battery cell during the discharge process. The history of the real-time maximal energy storage capacity of the battery cell may be stored as an identity resume of the battery cell, in a battery resume record device.

Abstract: Some implementations described herein include systems and techniques for fabricating a multi-dimension through silicon via structure in a three-dimensional integrated circuit device. The multi-dimension through silicon via structure includes a first columnar structure having a first width and a second columnar structure including a second width that is greater relative to the first width. The first columnar structure may include a low electrical capacitance and be configured for electrical signaling within the three-dimensional integrated circuit device. The second columnar structure may be configured to provide power to integrated circuitry of the three-dimensional integrated circuit device and also be configured to conduct heat through the three-dimensional integrated circuit device for thermal management of the three-dimensional integrated circuit device. Additionally, a pattern including the second columnar structure may be used for alignment purposes.

Abstract: A negative electrode structure applied to an aluminum battery includes a hole material layer and a metal plating layer. The metal plating layer is located on the hole material layer such that the capacity decay rate of the aluminum battery is less than 5% per cycle.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

Abstract: The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a search circuitry and a substitution check circuitry. The key generation circuitry is arranged operably to convert a first value of one byte corresponding to a plaintext, an intermediate encryption result, or a round key into a second value of a K-bit according to an 8-to-K lookup table, where K is an integer ranging from 10 to 15 and the second value comprises (K minus 8) bits of a Hamming parity. The substitution check circuitry is arranged operably to employ check formulae corresponding to the 8-to-K lookup table to determine whether an error is occurred during a conversion of the first value of the one byte into the second value of the K-bit, and output an error signal when finding the error, where a total amount of the formulae is K minus 8.

Abstract: A control method of a robotic arm is provided. The control method includes: setting a detection circuit, a comparing circuit and a switching circuit. The detection circuit detects the motion of the robotic arm to generate a detection signal. The comparing circuit compares the detection signal with a low threshold region and compares the detection signal with a high threshold region to generate a comparison signal. The switching circuit switches the robotic arm to a first motion mode or a second motion mode according to the comparison signal.

Abstract: Provided is a method for video decoding including: receiving a control variable enabling adaptive switch between motion vector refinement (MVR) offset sets; receiving an indication variable enabling adaptive switch between codeword tables that binarize offset magnitudes in the MVR offset sets under the coding level; partitioning the video block into a first and a second geometric partition; selecting an MVR offset set based on the control variable; receiving syntax elements to determine a first and second MVR offsets applied to the first and second geometric partitions from the selected MVR offset set; obtaining a first and second MVs from a candidate list for the first and the second geometric partition; calculating a first and second refined MVs based on the first and second MVs and the first and second MVR offsets; and obtaining prediction samples based on the first and second refined MVs.

Abstract: A gas infusion tank for a beverage machine includes a tank body defining a holding space for accommodating beverages. A mixing element includes a mixing chamber, an ascending pipe, and a descending pipe. A top of the ascending pipe is fluidly connected to the mixing chamber and a bottom of the ascending pipe has a liquid inlet. The liquid inlet is fluidly connected to the holding space. A top of the descending pipe is fluidly connected to the mixing chamber and a bottom of the descending pipe includes a liquid outlet in fluid communication with the nozzle. A gas intake hole connects the holding space with the mixing chamber.

Abstract: Provided in the present disclosure are a paging method and apparatus, and a storage medium. The paging method includes: determining that entry into a target sleep state is required, and transmitting an assisted paging request to at least one second terminal device; and determining that a target terminal device of the at least one second terminal device accepts the assisted paging request, and entering the target sleep state.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.