Patents by Inventor Wei Chen

Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12153868
    Abstract: An integrated circuit includes a plurality of metal lines extending along a first direction, the plurality of metal lines being separated, in a second direction perpendicular to the first direction, by integral multiples of a nominal minimum pitch. The integrated circuit further includes a plurality of standard cells, at least one of the plurality of standard cells having a cell height along the second direction being a non-integral multiple of the nominal minimum pitch.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Chun-Fu Chen, Ting-Wei Chiang, Hui-Zhong Zhuang, Hsiang-Jen Tseng
  • Patent number: 12152303
    Abstract: An intersecting module is provided. The intersecting module includes a plurality of internal ventilating plates. The internal ventilating plates have a plurality of orifices and include a first group of internal ventilating plates, a second group of internal ventilating plates, and a third group of internal ventilating plates arranged along a longitudinal direction. The second group of internal ventilating plates are positioned between the first group of internal ventilating plates and the third group of internal ventilating plates in the longitudinal direction. The first group of internal ventilating plates and the second group of internal ventilating plates are arranged in a staggered manner, and the second group of internal ventilating plates and the third group of internal ventilating plates are also arranged in a staggered manner.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Syuan Lan, Chia-Wei Chen
  • Patent number: 12155328
    Abstract: A multi-axis servo control system includes a plurality of motors and a plurality of drive control apparatuses. The drive control apparatuses are connected to each other through an external field bus. Each drive control apparatus includes a control unit and a plurality of drive units. The drive units are connected to the control unit in series by a plurality of local buses to form a series-connected communication loop of sequentially transmitting data. Each drive unit controls at least one of the motors. The control unit receives multi-axis position commands through the external field bus, and the drive units correspondingly receive multi-axis commands through the local buses so as to control the motors in a decentralization manner.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: November 26, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chien-Da Chen, I-Hsuan Tsai, Chia-Hua Lee, Ching-Wei Huang
  • Patent number: 12156325
    Abstract: A package carrier includes a circuit structure layer and a heat-conducting element. The circuit structure layer includes a notch portion. The heat-conducting element includes a first heat-conducting portion and a second heat-conducting portion vertically connected to the first heat-conducting portion. The notch portion exposes the first heat-conducting portion, and an outer surface of the second heat-conduction portion is aligned with a side surface of the circuit structure layer.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: November 26, 2024
    Assignee: Unimicron Technology Corp.
    Inventors: Ming-Hao Wu, Hsuan-Wei Chen, Chi-Chun Po
  • Patent number: 12156189
    Abstract: Aspects are presented which enable a UE to determine a supplementary uplink (SUL) configuration for an uplink cancellation indication (ULCI) for cancelling uplink communications in SUL. The UE receives from a base station a first configuration associated with a first block of an ULCI and associated with at least one of a SUL carrier a non-supplementary uplink (NUL) carrier in a cell. The base station configures the UE with a second configuration associated with a second block of the ULCI and associated with a SUL carrier in the cell, and the UE determines the second configuration. The UE monitors the ULCI based on the first configuration and the second configuration.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: November 26, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Wei Yang, Seyedkianoush Hosseini, Seyed Ali Akbar Fakoorian, Wanshi Chen
  • Publication number: 20240387297
    Abstract: A semiconductor device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer. The conductive pad is between the interconnect layer and the conductive seed layer.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Hsien-Wen Liu, Hsien-Wei Chen
  • Publication number: 20240383567
    Abstract: A hub motor includes an axle, a stator, a rotor, a planetary gear set, a casing, and a sleeve. The axle is fixed to a frame of the bicycle and has a first end and a second end. The stator is fixed to the axle. The rotor is rotatably sleeved on the axle and rotates around the stator. The planetary gear set has a ring gear. The casing is rotatably sleeved on the axle, connected to the rotor through the planetary gear set, and driven by the rotor, and rotates around the rotor and the axle. The casing has an accommodating space, an axle hole, and an opening. The accommodating space accommodates the stator and the rotor and is communicated with the opening. The axle is arranged to pass through the accommodating space, the axle hole, and the opening along an axial direction of a rotating axis.
    Type: Application
    Filed: September 25, 2023
    Publication date: November 21, 2024
    Inventors: CHUN-WEI CHEN, CHANG-CHUN KAO, SHANG-FENG LIN
  • Publication number: 20240383093
    Abstract: Embodiments of the present disclosure relate a CMP tool and methods for planarization a substrate. Particularly, embodiments of the present disclosure provide a substrate transporter for use in a CMP tool. The transporter may be used transport and/or carry substrates among various polishers and cleaners in a CMP tool while preventing the substrates from drying out during transportation. By keeping surfaces of the substrates wet during substrate waiting time or idle time in the CMP tool, embodiments of the present disclosure prevent many types of defects, such as byproducts, agglomerated abrasives, pad debris, slurry residues, from accumulate on the substrate surface during CMP processing, thus improve yields and device performance.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 21, 2024
    Inventors: Te-Chien HOU, Chih Hung CHEN, Kang HUANG, Wen-Pin LIAO, Shich-Chang SUEN, Kei-Wei CHEN
  • Publication number: 20240386327
    Abstract: Methods, systems, and computer program products are provided for embedding learning to provide uniformity and orthogonality of embeddings. A method may include receiving a dataset that includes a plurality of data points including a first plurality of data points having a first classification and a second plurality of data points having a second classification, generating a first normalized class mean vector of the first plurality of data instances having the first classification, generating a second normalized class mean vector of the second plurality of data instances having the second classification, performing a class rectification operation on the first plurality of data instances having the first classification and the second plurality of data instances having a second classification, and generating embeddings of the dataset based on original embedding space projections of the dataset.
    Type: Application
    Filed: May 17, 2024
    Publication date: November 21, 2024
    Inventors: Yan Zheng, Prince Osei Aboagye, Michael Yeh, Junpeng Wang, Huiyuan Chen, Xin Dai, Liang Wang, Wei Zhang
  • Publication number: 20240383568
    Abstract: A hub motor includes an axle, a stator, a rotor, a casing, a sleeve, and a torque sensor. The axle is fixed to a frame of the bicycle and has a first end and a second end. The stator is fixed to the axle. The rotor is rotatably sleeved on the axle and rotates around the stator. The casing is rotatably sleeved on the axle and rotates around the rotor and the axle. The casing forms an accommodating space, a first perforation, an opening, and a side cover. The side cover closes the opening and has a second perforation. The accommodating space accommodates the stator and the rotor. The axle is arranged to pass through the casing and the side cover respectively through the first perforation and the second perforation. The sleeve is sleeved at the second end and connected to the side cover. The sleeve has an arrangement part.
    Type: Application
    Filed: October 12, 2023
    Publication date: November 21, 2024
    Inventors: CHUN-WEI CHEN, CHANG-CHUN KAO
  • Publication number: 20240387401
    Abstract: A method includes forming a first semiconductor device, wherein the first semiconductor device includes a top surface and a bottom surface, and wherein the first semiconductor device includes a metal layer having an exposed first surface. The method also includes forming a Electromagnetic Interference (EMI) layer over the top surface and sidewalls of the first semiconductor device, wherein the EMI layer electrically contacts the exposed first surface of the metal layer. The method also includes forming a molding compound over the EMI layer.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Chi-Hsi Wu, Hsien-Wei Chen, Li-Hsien Huang, Tien-Chung Yang
  • Publication number: 20240386331
    Abstract: A method and system are provided for generating a combined prediction using an ensemble machine learning system. The prediction may be used in risk assessment for payroll processing. A data point is received as input to a multitude of trained models. Each model is trained from a respective data subset of a disparate data. A model prediction this generated by each of a multitude of machine learning models. For each respective trained model, a trust score is generated based on a data sparseness metric of the data point and a feature importance vector of the respective model. The model predictions and trust scores are received as input to a meta-model that was trained from the trust score and the model prediction of the multitude of trained models over the respective data subset of the disparate data. A combined prediction is generated using the trained meta-model.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 21, 2024
    Applicant: Intuit Inc.
    Inventors: Yue Yu, Wei Wang, Aditi Das, Luna Wang, Lei Chen, Atanu Roy, Junyan Ge, Shenlu Chen
  • Publication number: 20240387312
    Abstract: A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Chia-Cheng Tsai, Kuo-Hsin Ku, Chien-Wei Chang, Chun Yan Chen, Chia-Chi Chung
  • Publication number: 20240387206
    Abstract: A pickup apparatus for separating a semiconductor die adhered on an adhesive film therefrom includes a frame, an UV light emitting element, and a collector element. The frame is configurated to hold the adhesive film adhered with the semiconductor die thereon. The UV light emitting element is disposed inside the frame, where the adhesive film is disposed between the semiconductor die and the UV light emitting element. The collector element is disposed over the frame.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu
  • Publication number: 20240387338
    Abstract: A package assembly includes a package substrate including a molding material layer and a plurality of substrate portions embedded in the molding material layer, a redistribution layer (RDL) structure on the package substrate, and a plurality of semiconductor devices on the RDL structure.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Inventors: Hsien-Wei CHEN, Jing-Ye JUANG, Shin-Puu JENG
  • Publication number: 20240387248
    Abstract: A patterning process that can be utilized in order to help form conductive lines within a dielectric layer of a metallization layer is provided. In an embodiment a first interfacial layer is patterned a first time, the first interfacial layer being located over a first hard mask layer over a dielectric layer, the patterning the first interfacial layer the first time forming a first opening, which is filled with a first dielectric material. The first interfacial layer is patterned a second time, the patterning the first interfacial layer the second time forming second openings in the first interfacial layer, at least one of the second openings exposing the first dielectric material. The first dielectric material is removed, and the dielectric layer is patterned a second time after the removing the first dielectric material using the first interfacial layer as a mask, the patterning the dielectric layer extending the second openings.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Kuan-Wei Huang, Yu-Yu Chen
  • Publication number: 20240387366
    Abstract: Disclosed are methods of manufacturing semiconductor devices that include the operations of forming an isolation structure in a semiconductor substrate, forming an active region adjacent the isolation structure, forming at least two primary polysilicon structures over the active region, the primary polysilicon structures defining a contacted polysilicon pitch (CPP), and forming a secondary polysilicon structure over the isolation structure. In some methods, the secondary polysilicon structure is further modified and/or replaced in order to provide additional functional elements on the semiconductor devices.
    Type: Application
    Filed: May 15, 2023
    Publication date: November 21, 2024
    Inventors: Yi-Ming LIN, Jhen-Wei CHEN, Ling-Sung WANG, Yu-Jen CHEN
  • Publication number: 20240387254
    Abstract: A semiconductor structure includes a via in contact with a conductive line and extending through a first etch stop layer, a first inter-metal dielectric layer, and a second etch stop layer. The second etch stop layer is disposed over the first inter-metal dielectric layer, and the first inter-metal dielectric layer is disposed over the first etch stop layer. The semiconductor structure also includes a trench in contact with the via and extending through an insulating layer and a second inter-metal dielectric layer. The second inter-metal dielectric layer is disposed over the insulating layer which is disposed over the second etch stop layer.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Han Chen, Shih-Yu Chang, Chien-Chih Chiu, Yi-Tang Chen, Da-Wei Lin
  • Publication number: 20240387346
    Abstract: Embodiments include a device. The device includes an interposer, a package substrate, and conductive connectors bonding the package substrate to the interposer. Each of the conductive connectors have convex sidewalls. A first subset of the conductive connectors are disposed in a center of the package substrate in a top-down view. A second subset of the conductive connectors are disposed in an edge/corner of the package substrate in the top-down view. Each of the second subset of the conductive connectors have a greater height than each of the first subset of the conductive connectors.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 21, 2024
    Inventors: Chih-Chiang Tsao, Chao-Wei Chiu, Hsin Liang Chen, Chia-Shen Cheng, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Publication number: 20240387515
    Abstract: An integrated circuit (IC) device includes a substrate having a front side, a back side below the front side, and first functional circuitry and a first electrostatic discharge (ESD) clamp circuit on the front side of the substrate. The IC device further includes a first connection tower that extends below the back side of the substrate and is connected to an input/output pad below the back side of the substrate, and one or more first front side conductors and one or more first front side vias which connect the first buried connection tower to the first functional circuitry and to the first ESD clamp circuit.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chia-Wei HSU, Bo-Ting CHEN, Jam-Wem LEE