Patents by Inventor Wei Chen

Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136420
    Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.
    Type: Application
    Filed: December 1, 2022
    Publication date: April 25, 2024
    Applicant: AUO Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
  • Publication number: 20240138139
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.
    Type: Application
    Filed: July 17, 2023
    Publication date: April 25, 2024
    Inventors: SHIH-FAN KUAN, WEI-CHEN PAN, YU-TING LIN, HUEI-RU LIN
  • Publication number: 20240138060
    Abstract: Embodiments of this application provide a printed circuit board, including a core board and a substrate. The core board covers and is disposed on an outer surface of the substrate. The core board includes a first conductive layer, a second conductive layer, and a first dielectric layer. The first conductive layer is located on a side that is of the core board and that is away from the substrate, the second conductive layer is located on a side that is of the core board and that is close to the substrate, and the first dielectric layer is located between the first conductive layer and the second conductive layer, and includes a flexible dielectric layer whose Young's modulus is less than or equal to a preset Young's modulus.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 25, 2024
    Inventors: Wei TAO, Yupeng JIN, Yalei SANG, Zhenyu CHEN, Wusiman ZAIMURAN
  • Publication number: 20240134180
    Abstract: An optical device and the prism module thereof are provided. The prism module includes a first prism, a second prism, and a third prism. The second prism is disposed beside the first prism. The third prism is adhered to the second prism. First light enters the first prism, is reflected plural times in the first prism, enters the second prism, and is emitted from the second prism. Second light enters the second prism, is reflected plural times in the second prism, and is emitted from the second prism. Third light sequentially passes through the third prism and the second prism, enters the first prism, is reflected plural times in the first prism, and is emitted from the first prism.
    Type: Application
    Filed: October 19, 2023
    Publication date: April 25, 2024
    Inventors: Fei Han, Xiao-Yao Zhang, Yue-Ye Chen, Ling-Wei Zhao, Jun-Wei Che, Hua-Tang Liu
  • Publication number: 20240138138
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 25, 2024
    Inventors: SHIH-FAN KUAN, WEI-CHEN PAN, YU-TING LIN, HUEI-RU LIN
  • Publication number: 20240131819
    Abstract: A thermally conductive board includes a first metal layer, a second metal layer, and a thermally conductive layer. The material of the first metal layer includes copper, and the first metal layer has a first top surface and a first bottom surface opposite to the first top surface. A first metal coating layer covers the first bottom surface. The material of the second metal layer includes copper, and the second metal layer has a second top surface and a second bottom surface opposite to the second top surface. A second metal coating layer covers the second top surface and faces the first metal coating layer. The thermally conductive layer is an electrically insulator laminated between the first metal coating layer and the second metal coating layer.
    Type: Application
    Filed: May 3, 2023
    Publication date: April 25, 2024
    Inventors: KAI-WEI LO, WEN-FENG LEE, HSIANG-YUN YANG, KUO-HSUN CHEN
  • Publication number: 20240136297
    Abstract: A multi-chip interconnection package structure with a heat dissipation plate and a preparation method thereof are provided. The multi-chip interconnection package structure with a heat dissipation plate includes a fine circuit layer, at least one die, a heat dissipation plate, a plastic package body, and a package circuit layer, the heat dissipation plate is provided on the fine circuit layer, and is mounted on a side of the die away from the fine circuit layer, the plastic package body wraps the die and the heat dissipation plate, and the package circuit layer is provided on the plastic package body.
    Type: Application
    Filed: February 22, 2023
    Publication date: April 25, 2024
    Applicant: Institute of Semiconductors, Guangdong Academy of Sciences
    Inventors: Yingqiang YAN, Chuan HU, Yao WANG, Wei ZHENG, Zhitao CHEN
  • Publication number: 20240132925
    Abstract: The invention provides a method for preparing pyrrolidone, and the invention provides a method for catalytically preparing pyrrolidone with ?-aminobutyric acid in the presence of carnitine-CoA ligase CaiC. The carnitine-CoA ligase CaiC has an amino acid sequence as shown in SEQ ID NO:1. The ligase has catalytic activity in the cyclization of ?-aminobutyric acid to produce pyrrolidone. The carnitine-CoA ligase provided in the present invention affords a yield of pyrrolidone of 3.26 g/L and a molar yield of 39.53% in 24 h when ?-aminobutyric acid is used as a substrate, thus reducing the production period, improving the production of pyrrolidone, and accelerating the industrialization process of producing pyrrolidone by enzymatic conversion method.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Inventors: Jing WU, Xuling JIANG, Liming LIU, Wei SONG, Yiwen ZHOU, Xiulai CHEN, LIU Jia, Cong GAO
  • Publication number: 20240136933
    Abstract: A back-end energy storage isolation fly-back conversion apparatus (10) includes a return switch (Q1), a driving switch (Q2), an energy storage capacitor (Cs), a transformer (Ti), a resonant inductor (Lr), a first rectifier (104), an output capacitor (Cout), and a controller (116). The transformer (T1) includes a primary-side winding (Lm) and a secondary-side first winding (102). The return switch (Q1) is turned on by the controller (116), so that the energy storage capacitor (Cs) is charged by a primary-side current (I1) flowing through the resonant inductor (Lr), the primary-side winding (Lm), and the return switch (Q1), and the secondary-side first winding (102) is powered by the primary-side current (I1). When the primary-side current (I1) becomes negative, the energy storage capacitor (Cs) discharges through the return switch (Q1) and the primary-side winding (Lm) and continuously supplies power to the secondary-side first winding (102).
    Type: Application
    Filed: October 15, 2023
    Publication date: April 25, 2024
    Inventors: Wei-Chen LIANG, Pin CHANG
  • Publication number: 20240132923
    Abstract: Provided is a recombinant microorganism including at least two genes for producing itaconic acid and its derived monomers, and the at least two genes are located on the same expression vector. The at least two genes include one encoding cis-aconitic acid decarboxylase and the other one encoding aconitase, and the genome of the recombinant microorganism includes a gene encoding the molecular chaperone protein GroELS. Also provided is a method for producing itaconic acid by using the microorganism.
    Type: Application
    Filed: March 22, 2023
    Publication date: April 25, 2024
    Inventors: I-Son NG, Jo-Shu CHANG, Chuan-Chieh HSIANG, Yeong-Chang CHEN, Yu-Chiao LIU, Chia-Wei TSAI
  • Publication number: 20240136226
    Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Li-Wei CHU, Ying-Chi SU, Yu-Kai CHEN, Wei-Yip LOH, Hung-Hsu CHEN, Chih-Wei CHANG, Ming-Hsing TSAI
  • Patent number: 11966628
    Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: April 23, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wei-Chen Wang, Han-Wen Hu, Yung-Chun Li, Huai-Mu Wang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 11968206
    Abstract: A mechanism for building decentralized computer applications that execute on a distributed computing system. The present technology works within a web browser, client application, or other software and provides access to decentralized computer applications through the browser. The present technology is non-custodial, wherein a public-private key pair, which represents user identity, is created on a client machine and then directly encrypted by a third-party platform without relying on one centralized computing system.
    Type: Grant
    Filed: September 15, 2023
    Date of Patent: April 23, 2024
    Assignee: Magic Labs, Inc.
    Inventors: Fei-Yang Jen, Yi Wei Chen, Jaemin Jin, Hanyu Xue, Wentao Liu, Shang Li
  • Patent number: 11967119
    Abstract: The present disclosure relates to systems and methods for coding. The methods may include receiving at least two contexts, for each of the at least two contexts, obtaining at least one coding parameter corresponding to the context from at least one lookup table, determining a probability interval value corresponding to the context based on a previous probability interval value and the at least one coding parameter, determining a normalized probability interval value corresponding to the context by performing a normalization operation on the probability interval value, determining a probability interval lower limit corresponding to the context based on a previous probability interval lower limit and the at least one coding parameter, determining a normalized probability interval lower limit corresponding to the context by performing the normalization operation on the probability interval lower limit, and outputting at least one byte based on the normalized probability interval lower limit.
    Type: Grant
    Filed: December 12, 2021
    Date of Patent: April 23, 2024
    Assignee: ZHEJIANG DAHUA TECHNOLOGY CO., LTD.
    Inventors: Pan Yu, Zhuqing Zhu, Qi Chen, Wei Fang, Yinchang Yang
  • Patent number: 11966124
    Abstract: A display panel includes a display region and a photoelectric sensing region which includes a light transmitting region and a frame region surrounding the light transmitting region; the frame region includes a first region surrounding the light transmitting region, a second region on a side of the first region away from the light transmitting region and surrounding the first region, and a third region between the second region and the display region. The spacers are in an array and in the display region but not in the light transmitting region. A plurality of first support pillars are in the first region, arranged around the light transmitting region, and spaced from each other. A plurality of second support pillars are in the second region, around the second region, and spaced from each other. A plurality of third support pillars are in the third region in an array.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: April 23, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Kai Chen, Yanqing Chen, Ruichao Liu, Jie Tong, Xiaofeng Zhang, Weida Qin, Ning Wang, Yan Wang, Wei Li, Haoyi Xin
  • Patent number: 11968817
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Patent number: 11968160
    Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums which provide for sidebar communication threads forked from, or related to, a principal thread. Messages in the sidebar communication thread may include a history of the principal thread, including one or more messages from the principal thread, and may include a proposed principal thread message that is the subject of the sidebar thread discussion. The sidebar thread may also include sidebar thread messages that carries the conversation of the sidebar thread participants. Once a termination condition is reached for the sidebar thread, the sidebar thread terminates and either the proposed principal thread message (as potentially modified by participants of the sidebar thread) becomes an accepted principal thread message and it is posted to the principal thread as if it was sent by the sidebar initiator or no message is posted (e.g., the proposed principal thread message is rejected).
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: April 23, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Amer Aref Hassan, Wei-Chen Chen
  • Patent number: 11966241
    Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Neng Chen, Yen-Lin Liu, Chia-Wei Hsu, Jo-Yu Wu, Chang-Fen Hu, Shao-Yu Li, Bo-Ting Chen
  • Patent number: 11967563
    Abstract: A Fan-Out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yan-Fu Lin, Chen-Hua Yu, Meng-Tsan Lee, Wei-Cheng Wu, Hsien-Wei Chen
  • Patent number: D1024051
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: Hui-Jung Huang, Hong-Kuan Li, I-Lun Li, Ling-Mei Kuo, Kuan-Ju Chen, Fang-Ying Huang, Kai-Hung Huang, Szu-Wei Yang, Kai-Teng Cheng