Abstract: A heat dissipation assembly includes a condenser, an evaporator, a vapor conduit, and a liquid conduit. The condenser has a condensing chamber therein. Two ends of the vapor conduit are respectively connected to the condenser and the evaporator. Two ends of the liquid conduit are respectively connected to the condenser and the evaporator. A geometric center of the liquid conduit in the condensing chamber is lower than or equal to a geometric center of the condensing chamber.

Abstract: A method includes forming in sequence a metallic capping layer and a dummy gate electrode layer over a semiconductor substrate; patterning the metallic capping layer and the dummy gate electrode layer to form a first stacked structure including a first portion of the metallic capping layer and a first portion of the dummy gate electrode layer; forming a plurality of first gate spacers on opposite sides of the first stacked structure; removing the first portion of the dummy gate electrode layer to expose the first portion of the metallic capping layer; and forming a first work function metal layer on the first portion of the metallic capping layer.

Abstract: A method includes following steps. A dummy gate structure is formed across a first portion of a semiconductor fin. A doped semiconductor layer is formed across a second portion of the semiconductor fin. A dielectric layer is formed across the doped semiconductor layer. An interface between the dielectric layer and the doped semiconductor layer substantially conforms to a profile of a combination of a top surface and sidewalls of the semiconductor fin. The dummy gate structure is replaced with a metal gate structure.

Abstract: Systems and methods for in-die metrology using target design patterns are provided. These systems and methods include selecting a target design pattern based on design data representing the design of an integrated circuit, providing design data indicative of the target design pattern to enable design data derived from the target design pattern to be added to second design data, wherein the second design data is based on the first design data. Systems and methods can further include causing structures derived from the second design data to be printed on a wafer, inspecting the structures on the wafer using a charged-particle beam tool, and identifying metrology data or process defects based on the inspection. In some embodiments the systems and methods further include causing the charged-particle beam tool, the second design data, a scanner, or photolithography equipment to be adjusted based on the identified metrology data or process defects.

Abstract: Disclosed herein is a method of automatically obtaining training images to train a machine learning model that improves image quality. The method may comprise analyzing a plurality of patterns of data relating to a layout of a product to identify a plurality of training locations on a sample of the product to use in relation to training the machine learning model. The method may comprise obtaining a first image having a first quality for each of the plurality of training locations, and obtaining a second image having a second quality for each of the plurality of training locations, the second quality being higher than the first quality. The method may comprise using the first image and the second image to train the machine learning model.

Abstract: A wafer probe station includes a first shielding box, a chuck, a stage, a second shielding box, an electronic testing instrument, a manipulator and a cable. The first shielding box has a first chamber. The chuck is located in the first chamber to hold a device under test. The stage connects to the chuck to move the chuck. The second shielding box is outside the first shielding box and forms a second chamber with the first shielding box. The first and the second shielding boxes shield against an electromagnetic field. The electronic testing instrument is inside the second chamber. The manipulator is outside the first shielding box and has a probe arm penetrating into the first chamber. The probe arm is movable by the manipulator to hold a probe to contact the device under test. The cable connects between the electronic testing instrument and the probe.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes following steps. A MEOL structure is formed on an etch stop layer. A patterned masking layer with at least one opening is formed on the MEOL structure and a first etching process is performed to form a trench in the MEOL structure. A second etching process is performed to modify at least one sidewall of the trench.

Abstract: The present application provides a single photon source device, a preparation method thereof, and applications of the same. The single photon source device includes a first electrode layer, a first carrier transport layer, a quantum dot light-emitting layer, a second carrier transport layer and a second electrode layer which are stacked in sequence, and the quantum dot light-emitting layer comprises an insulating material and quantum dots dispersed in the insulating material, neighbor distance of at least a part of the quantum dots is greater than or equal to the central wavelength of the luminescent spectrum of quantum dots.

Abstract: A memory device includes a memory array having multiple nonvolatile memory cells that stores data as a set or a reset state of the memory cells. The nonvolatile memory cells can be resistance-based memory, which stores data based on resistive state of the memory cells. A controller coupled to the memory array periodically samples set and reset margins for memory cells of the memory array. Responsive to detection of a change in a margin, the system can adaptively adjust a preset electrical setting used to differentiate between a set state and a reset state.

Abstract: An inspection method includes the following steps: identifying a plurality of patterns within an image; and comparing the plurality of patterns with each other for measurement values thereof. The above-mentioned inspection method uses the pattern within the image as a basis for comparison; therefore, measurement values of the plurality of pixels constructing the pattern can be processed with statistical methods and then compared, and the false rate caused by variation of a few pixels is decreased significantly. An inspection system implementing the above-mentioned method is also disclosed.

Abstract: A method includes forming a gate dielectric layer over a semiconductor substrate, forming a first metal element-containing layer over the gate dielectric layer, and thermal soaking the first metal element-containing layer in a first gas, such that a constituent of the first gas is diffused into the first metal element-containing layer.

Abstract: A fingerprint module, comprising: a first part comprising a sensor, and a cover glass disposed on the sensor; and a second part comprising a light guide plate, and a LED disposed aside the light guide plate, wherein the first part and the second part are separate. More degree of freedom of the fingerprint module achieved in assembly.

Abstract: A method for aligning a wafer image with a reference image, comprising: searching for a targeted reference position on the wafer image for aligning the wafer image with the reference image; and in response to a determination that the targeted reference position does not exist: defining a current lock position and an area that encloses the current lock position on the wafer image; computing an alignment score of the current lock position; comparing the alignment score of the current lock position with stored alignment scores of positions previously selected in relation to aligning the wafer image with the reference image; and aligning the wafer image with the reference image based on the comparison.

Abstract: A heat dissipation assembly includes a condenser, an evaporator, a vapor conduit, and a liquid conduit. The condenser has a condensing chamber therein. Two ends of the vapor conduit are respectively connected to the condenser and the evaporator. Two ends of the liquid conduit are respectively connected to the condenser and the evaporator. A geometric center of the liquid conduit in the condensing chamber is lower than or equal to a geometric center of the condensing chamber.

Abstract: A method includes forming a channel region on a semiconductor substrate. An interfacial layer is formed on the channel region. The interfacial layer is treated with trimethyl aluminum (TMA). A high-k dielectric layer is formed on the interfacial layer after treating the interfacial layer with TMA. A gate electrode is formed on the high-k dielectric layer. The treating the interfacial layer with TMA and forming the high-k dielectric layer are performed in the same chamber. The interfacial layer is annealed before treating the interfacial layer with TMA. The annealing the interfacial layer and treating the interfacial layer with TMA are performed in different chambers.

Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.

Abstract: A calibration method for calibrating the position error in the point of interest induced from the stage of the defect inspection tool is achieved by controlling the deflectors directly. The position error in the point of interest is obtained from the design layout database.

Abstract: An improved charged particle beam inspection apparatus, and more particularly, a particle beam apparatus for inspecting a wafer including an improved scanning mechanism for detecting fast-charging defects is disclosed. An improved charged particle beam inspection apparatus may include a charged particle beam source that delivers charged particles to an area of the wafer and scans the area. The improved charged particle beam apparatus may further include a controller including a circuitry to produce multiple images of the area over a time sequence, which are compared to detect fast-charging defects.

Abstract: Systems and methods for optimal electron beam metrology guidance are disclosed. According to certain embodiments, the method may include receiving an acquired image of a sample, determining a set of image parameters based on an analysis of the acquired image, determining a set of model parameters based on the set of image parameters, generating a set of simulated images based on the set of model parameters. The method may further comprise performing measurement of critical dimensions on the set of simulated images and comparing critical dimension measurements with the set of model parameters to provide a set of guidance parameters based on comparison of information from the set of simulated images and the set of model parameters. The method may further comprise receiving auxiliary information associated with target parameters including critical dimension uniformity.

Abstract: A method includes forming in sequence a metallic capping layer and a dummy gate electrode layer over a semiconductor substrate; patterning the metallic capping layer and the dummy gate electrode layer to form a first stacked structure including a first portion of the metallic capping layer and a first portion of the dummy gate electrode layer; forming a plurality of first gate spacers on opposite sides of the first stacked structure; removing the first portion of the dummy gate electrode layer to expose the first portion of the metallic capping layer; and forming a first work function metal layer on the first portion of the metallic capping layer.