Patents by Inventor Wei Fang

Wei Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11151976
    Abstract: A method and system for operating a signal filter device are provided in the present disclosure. The signal filter device may include M adaptive filters, M first analysis filters, M second analysis filters, and a controller. M may be an integer above two. The method may include generating, by the M first analysis filters, M first sub-band signals based on an input signal. The method may also include generating, by the M second analysis filters, M second sub-band signals based on a reference signal. The method may further include adjusting, by the controller, the working states of the M adaptive filters based on correlations between the M first sub-band signals and the M second sub-band signals.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: October 19, 2021
    Assignee: ZHEJIANG DAHUA TECHNOLOGY CO., LTD.
    Inventors: Zhiyong Sun, Qi Chen, Wei Fang
  • Patent number: 11147748
    Abstract: The present invention is directed to a composition of temporary crown materials, comprising a powder reagent and a liquid reagent; wherein the powder reagent comprises PMMA and an initiator, and the liquid reagent comprises MMA, a catalyst, and a plasticizer; wherein the plasticizer is a citrate ester compound. The composition of temporary crown materials of the present invention has high hardness, high toughness, high flexural strength and excellent biocompatibility.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: October 19, 2021
    Assignee: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY
    Inventors: Hsu-Wei Fang, Yuan-Min Lin, Meng-Chun Lin
  • Patent number: 11152348
    Abstract: An integrated circuit structure includes: a first plurality of cell rows extending in a first direction, each of which has a first row height and comprises a plurality of first cells disposed therein; and a second plurality of cell rows extending in the first direction, each of which has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction, and wherein the plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kam-Tou Sio, Jiann-Tyng Tzeng, Jack Liu, Yi-Chuin Tsai, Shang-Wei Fang, Sing-Kai Huang, Charles Chew-Yuen Young
  • Publication number: 20210303847
    Abstract: The embodiments of the disclosure provide a space recognition method, an electronic device and a non-transitory computer-readable storage medium. The method includes the following steps. Sensor data for detecting obstacle positions is obtained from a sensor associated with an electronic device. A plurality of coordinates respectively corresponding to the obstacle positions are generated based on the sensor data. Boundary line information of a space surrounding the electronic device is updated according to the coordinates until an optimization condition is met for each boundary line. A spatial range of the space surrounding the electronic device is identified based on the boundary line information. The spatial range is used to guide a movement of the electronic device.
    Type: Application
    Filed: February 19, 2021
    Publication date: September 30, 2021
    Applicant: ALi Corporation
    Inventors: Yu-Wei Fang, Shui Shih Chen, Chia Jui Kuo
  • Patent number: 11133998
    Abstract: A method, an apparatus, and a system for measuring a network delay are disclosed. The method includes: acquiring delay measurement information obtained by measuring a service flow by at least one target logical port TLP, where the delay measurement information includes: timestamp information, a service flow identifier, and a TLP identifier; and transmitting the delay measurement information to a measurement control point MCP, so that the MCP determines details about a network delay according to the timestamp information, the service flow identifier, and the TLP identifier. Embodiments of the present application further provide an apparatus and a system for measuring a network delay. Embodiments of the present application achieve direct and accurate delay measurement of a service flow in scenarios of point to point transmission or point to multipoint transmission on the network, and reflect details about a real delay of the service flow.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: September 28, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Wei Fang, Hongming Liu, Wenjun Chang
  • Publication number: 20210296507
    Abstract: A method includes following steps. A silicon germanium layer is formed on a substrate. A surface layer of the silicon germanium layer is oxidized to form an interfacial layer comprising silicon oxide and germanium oxide. The interfacial layer is nitridated. A metal gate structure is formed over the nitridated interfacial layer.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yu CHANG, Hsiang-Pi CHANG, Zi-Wei FANG
  • Patent number: 11126089
    Abstract: A method for determining corrections to features of a mask. The method includes obtaining (i) a pattern group for a design layout, and (ii) defect inspection data of a substrate imaged using the mask used in the patterning process for the design layout; determining, based on the defect inspection data, a defect map associated with the pattern group, wherein the defect map comprises locations of assist features having a relatively higher probability of being printed on the substrate compared to other patterns of the design layout; and determining, via simulating an optical proximity correction process using data associated with the defect map, corrections to the features of the mask.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: September 21, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Wei Fang, Lingling Pu, Zhichao Chen, Haili Zhang, Pengcheng Zhang
  • Publication number: 20210288166
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin extending from the semiconductor substrate, a gate structure extending across the semiconductor fin, and source/drain semiconductor layers on opposite sides of the gate structure. The source/drain semiconductor layers each have a first thickness over a top side of the semiconductor fin and a second thickness over a lateral side of the semiconductor fin. The first thickness and the second thickness have a difference smaller than about 20 percent of the first thickness.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Sheng HUANG, Hung-Chang SUN, I-Ming CHANG, Zi-Wei FANG
  • Publication number: 20210280679
    Abstract: A semiconductor device includes a substrate, a semiconductor fin extending from the substrate, a gate dielectric layer over the semiconductor fin, a metal nitride layer comprising a first portion over the gate dielectric layer and a second portion over the first portion, and a fill metal over the metal nitride layer. The second portion has an aluminum concentration greater than an aluminum concentration of the first portion.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 9, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ming LIN, Peng-Soon LIM, Zi-Wei FANG
  • Patent number: 11109047
    Abstract: A method for processing and transmitting multimedia signals received from a plurality of channels are provided. The method may include receiving at least two multimedia signals from a plurality of channels, and generating a composite multimedia digital signal by coding the multimedia signals in a frame format. At least one of the multimedia signals may include a video signal. The frame format may include an active zone and a blanking zone, the active zone may be configured to encode at least part of the multimedia signals, and the blanking zone may be configured to encode format information. The method may further include converting at least part of the encoded multimedia signals in the active zone into analog signals to generate a composite multimedia signal. The method may further include transmitting the composite multimedia signal to a receiving device via a transmission medium.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: August 31, 2021
    Assignee: ZHEJIANG XINSHENG ELECTRONIC TECHNOLOGY CO., LTD.
    Inventors: Zhaosheng Du, Genqiang Cui, Bingyun Lyu, Wei Fang
  • Patent number: 11100613
    Abstract: A method configured to be implemented on at least one image processing device for enhancing edges in images includes obtaining, by the at least one imaging processing device, image data of an image, wherein the image includes a plurality of pixels, and each of the plurality of pixels has a luminance value and a motion intensity value. The method also includes performing at least one filtering operation to the image to obtain, by the at least one imaging processing device, one or more filtered values for each pixel. The method further includes performing a first logical operation to the one or more filtered values of each pixel in the image to obtain, by the at least one imaging processing device, an edge value and an edge enhancement coefficient for each pixel in the image.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: August 24, 2021
    Assignee: ZHEJIANG DAHUA TECHNOLOGY CO., LTD.
    Inventors: Wei Li, Junjun Yu, Wei Fang
  • Patent number: 11094907
    Abstract: The present application provides a single photon source device, a preparation method thereof, and applications of the same. The single photon source device includes a first electrode layer, a first carrier transport layer, a quantum dot light-emitting layer, a second carrier transport layer and a second electrode layer which are stacked in sequence, and the quantum dot light-emitting layer comprises an insulating material and quantum dots dispersed in the insulating material, neighbor distance of at least a part of the quantum dots is greater than or equal to the central wavelength of the luminescent spectrum of quantum dots.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: August 17, 2021
    Assignees: Zhejiang University, Najing Technology Corporation Limited
    Inventors: Wei Fang, Xiaogang Peng, Yizheng Jin, Xing Lin, Xingliang Dai, Chaodan Pu
  • Publication number: 20210249407
    Abstract: An integrated circuit is disclosed, including a first conductive pattern and a second conductive pattern that are disposed in a first layer and extend in a first direction, at least one first conductive segment disposed in a second layer different from the first layer, and at least one via disposed between the first layer and the second layer. The at least one via is coupled between the at least one first conductive segment and one or both of the first conductive pattern and the second conductive pattern, at an output node of the integrated circuit. The at least one via comprises a tapered shape with a width that decreases from a first width to a second width narrower than the first width. The first width of the at least one via is greater than widths of the first conductive pattern and the second conductive pattern.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 12, 2021
    Inventors: Po-Chia LAI, Shang-Wei FANG, Meng-Hung SHEN, Jiann-Tyng TZENG, Ting-Wei CHIANG, Jung-Chan YANG, Stefan RUSU
  • Patent number: 11087954
    Abstract: A wafer inspection system includes a controller in communication with an electron-beam inspection tool. The controller includes circuitry to: acquire, via an optical imaging tool, coordinates of defects on a sample; set a Field of View (FoV) of the electron-beam inspection tool to a first size to locate a subset of the defects; determine a position of each defect of the subset of the defects based on inspection data generated by the electron-beam inspection tool during a scanning of the sample; adjust the coordinates of the defects based on the determined positions of the subset of the defects; and set the FoV of the electron-beam inspection tool to a second size to locate additional defects based on the adjusted coordinates.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 10, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Wei Fang, Joe Wang
  • Publication number: 20210241449
    Abstract: A method for correcting metrology data of a patterning process. The method includes obtaining (i) metrology data of a substrate subjected to the patterning process and (ii) a quality metric (e.g., a focus index) that quantifies a quality of the metrology data of the substrate; establishing a correlation between the quality metric and the metrology data; and determining a correction to the metrology data based on the correlation between the quality metric and the metrology data.
    Type: Application
    Filed: August 14, 2019
    Publication date: August 5, 2021
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Fuming WANG, Stefan HUNSCHE, Wei FANG
  • Publication number: 20210206628
    Abstract: A semiconductor package structure includes a die paddle, a plurality of leads, an electronic component and a package body. Each of the plurality of leads is separated from the die paddle and has an inner side surface facing the die paddle. The electronic component is disposed on the die paddle. The package body covers the die paddle, the plurality of leads and the electronic component. The package body is in direct contact with a bottom surface of the die paddle and the inner side surface of the plurality of leads.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Hsuan TSAI, Lu-Ming LAI, Chien-Wei FANG, Ching-Han HUANG
  • Publication number: 20210210488
    Abstract: An integrated circuit device includes: a first fin structure disposed on a substrate in a first direction; a second fin structure disposed on the substrate and aligned in the first direction; a third fin structure disposed on the substrate and aligned in the first direction; and a first conductive line aligned in a second direction arranged to wrap a first portion, a second portion, and a third portion of the first fin structure, the second fin structure and the third fin structure, respectively. Each of the first fin structure, the second fin structure and the third fin structure has a same type dopant. A first distance between the first fin structure and the second fin structure is different from a second distance between the second fin structure and the third fin structure.
    Type: Application
    Filed: March 23, 2021
    Publication date: July 8, 2021
    Inventors: KAM-TOU SIO, SHANG-WEI FANG, JIANN-TYNG TZENG, CHEW-YUEN YOUNG
  • Publication number: 20210212193
    Abstract: A circuit board assembly is applied to the field of electronic communications technologies to resolve a prior-art heat dissipation problem of a circuit board. The circuit board assembly combines, on a second circuit board, low-speed signals transmitted between a plurality of I/O modules and an IC chip, and then transmits the combined low-speed signals to the IC chip by using a low-speed cable. A low-speed signal sent by the IC chip to the plurality of I/O modules is extended to a plurality of low-speed signals on the second circuit board, and then the plurality of low-speed signals are separately sent to the plurality of I/O modules. This may be applied to a scenario in which a relatively large quantity of electronic components need to be disposed on a circuit board.
    Type: Application
    Filed: January 22, 2021
    Publication date: July 8, 2021
    Inventors: Chaojun DENG, Fei MA, Wei FANG, Zhiwen YANG, Chungang LI, Shun HAO
  • Patent number: 11055831
    Abstract: A system and method for filling light for video images are provided. The method may include: obtaining, by at least one video processing device, a first image including a plurality of reference pixels and is associated with at least one brightness direction; for each of the plurality of reference pixels, obtaining, by the at least one video processing device, a reference brightness value; identifying, by the at least one video processing device, a target brightness direction from the at least one brightness direction; for each of the plurality of reference pixels, determining a brightness enhancement multiplier for the reference pixel based on the plurality of reference brightness values and locations of the plurality of reference pixels along the target brightness direction of the first image; and modifying, by the at least one video processing device, brightness of the first image at least based on the brightness enhancement multipliers.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: July 6, 2021
    Assignee: ZHEJIANG DAHUA TECHNOLOGY CO., LTD.
    Inventors: Yong Qian, Junjun Yu, Wei Fang
  • Patent number: 11043356
    Abstract: A calibration method for calibrating the position error in the point of interest induced from the stage of the defect inspection tool is achieved by controlling the deflectors directly. The position error in the point of interest is obtained from the design layout database.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: June 22, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Wei Fang, Kevin Liu, Fei Wang, Jack Jau, Zhaohui Guo