Abstract: A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a first substrate, a second substrate disposed over the first substrate and having a first surface facing away from the first substrate and a second surface facing the first substrate, a first component disposed on the first surface of the second substrate, a second component disposed on the second surface of the second substrate; and a support member covering the first component.

Abstract: A light emitting substrate is provided. The light emitting substrate includes a plurality of light emitting controlling units arranged in M rows and N columns, M is an integer equal to or greater than one, N is an integer equal to or greater than one. A respective column of the N columns of light emitting controlling units includes M number of groups of second voltage signal lines, a respective group of the M number of groups of second voltage signal lines connected to a respective one of the M number of light emitting controlling units, the respective group of the M number of groups of second voltage signal lines including k number of second voltage signal lines, k is an integer equal to or greater than one.

Abstract: Electronic design automation (EDA) of the present disclosure logically places components of the electronic circuitry onto an electronic design real estate to determine an architectural design placement for the electronic circuitry. The EDA evaluates a metaheuristic algorithm starting with an initial placement of components of the electronic circuitry onto the electronic design real estate to provide multiple possible placements for placing these components of the electronic circuitry onto the electronic design real estate. The EDA utilizes the multiple possible placements of the metaheuristic algorithm to train one or more probabilistic functions of a model-based reinforcement learning (RL) algorithm. The EDA evaluates the model-based RL algorithm utilizing the one or more probabilistic functions to determine the architectural design placement.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

Abstract: A light emitting substrate, a method of driving a light emitting substrate, and a display device are provided. The light emitting substrate includes a plurality of light emitting units arranged in an array. Each light emitting unit includes a driving circuit, a plurality of light emitting elements, and a driving voltage terminal. The plurality of light emitting elements are sequentially connected in series and connected between the driving voltage terminal and the output terminal of the driving circuit. The driving circuit is configured to output a relay signal through the output terminal in a first period according to a first input signal received by the first input terminal and a second input signal received by the second input terminal, and supply a driving signal to the plurality of light emitting elements sequentially connected in series through the output terminal in a second period.

Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Abstract: The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.

Abstract: A plasma enhanced atomic layer deposition (PEALD) system includes a process chamber. A target substrate is supported in the process chamber. A grid is positioned in the process chamber above the target substrate. The grid includes a plurality of apertures extending from a first side of the grid to a second side of the grid. During a PEALD process, a plasma generator generates a plasma. The energy of the plasma is reduced by passing the plasma through the apertures in the grid prior to reacting the plasma with the target substrate.

Abstract: A conductive textile includes a base cloth and a conductive film disposed on the base cloth. The conductive film includes a polyurethane resin and a silver bearing conductor, in which a content of the silver bearing conductor is 55 parts by weight to 80 parts by weight, and a content of the polyurethane resin is 8 parts by weight to 12 parts by weight.

Abstract: A method includes forming an active fin using a hard mask as an etching mask, wherein the active fin comprises a source region, a drain region, and a channel region, the hard mask remains over the active fin after etching the semiconductive substrate, and the hard mask has a first portion vertically overlapping the source region of the active fin, a second portion vertically overlapping the channel region of the active fin, and a third portion vertically overlapping the drain region of the active fin. A sacrificial gate is formed over the second portion of the hard mask and the channel region of the active fin. The first and third portions of the hard mask are etched. After etching the first and third portions of the hard mask, a gate spacer is formed extending along sidewalls of the sacrificial gate, and the sacrificial gate is replaced with a replacement gate.

Abstract: An extreme ultraviolet (EUV) mask, includes a substrate, a reflective multilayer stack on the substrate, and a multi-layer capping feature on the reflective multilayer stack. The multi-layer capping feature includes a first capping layer including a material containing an element having a first carbon solubility and a second capping layer including a material containing an element having a second carbon solubility. The first carbon solubility being different from the second carbon solubility. In some embodiments an element of the material of the first capping layer and an element of the second capping layer have extinction coefficients for EUV having a wavelength of 13.5 nm that are different.

Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

Abstract: An electronic device including two bodies and at least one hinge structure including a connecting assembly and two rotating assemblies is provided. Each rotating assembly is rotatably connected to the connecting assembly and includes a bracket having at least one first sliding slot, a translation member translatably arranged on the bracket and having at least one second sliding slot, and a sliding member having at least one pillar penetrating the first second sliding slots at an overlapping position. The first and second sliding slots are inclined to each other and partially overlapped at the overlapping position. The two bodies are respectively connected to the sliding members. When each rotating assembly rotates, the connecting assembly guides the translation member to translate relative to the bracket to displace the overlapping position and drive the pillar to slide along the first and second slots to move the sliding member and the corresponding body.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: A projection optical system with a concave reflector in the projection lens, comprising: an image source; a lens group; a reflector; an image and an aperture, the lens group and the reflector form multiple optical paths between the image and image source, each optical path has a chief ray and a marginal ray, the chief ray of one of the optical paths forms a chief ray of a paraxial image height at the part where image source be near to the optical axis, the chief ray of another one of the optical paths forms a marginal ray of an off-axis image height at the part where image source be far from the optical axis; wherein 2.2<F1/F2<3.0; 8<IMH/TR/Fno<19; 5<IMH*T1/T2<8. whereby the optimal optical performance of resolving power and optical path interference allowance will be achieved.

Abstract: An optical filter structure of an arbitrary combination of UV, R, G, B, and IR includes a substrate and a filter layer. The substrate is a wafer semiconductor sensor device and a product of light-transmitting device. The filter layer is formed on a surface of the substrate and is formed of a plurality of basic units arranged in an array. Each of the basic units includes a plurality of pixel filter films formed through vacuum coating, and the plurality of pixel filter films include an arbitrary combination of multiple ones of a UV pixel filter film, an R pixel filter film, a G pixel filter film, a B pixel filter film, and an IR pixel filter film, such that the plurality of pixel filter films allow light of corresponding wavelengths to pass therethrough.

Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.

Abstract: A fixing mechanism is applied to an interface card assembly and an electronic apparatus. The fixing mechanism includes a movable window and an operation component. The movable window is slidably disposed on a casing of the interface card assembly. The operation component has a fixed end and a free end opposite to each other. The fixed end is disposed on the movable window. The free end is detachably engaged with the casing to position the movable window. The movable window is positioned on one of a first region and a second region of the casing for respectively fixing interface cards with different sizes to the casing.

Abstract: The disclosure provides an eye state assessment method and an electronic device. The method includes: obtaining an optic disc image area from a first fundus photography and generating multiple optic cup-to-disc ratio assessment results by multiple first models based on the optic disc image area; obtaining a first assessment result of an eye based on the optic cup-to-disc ratio assessment results; performing multiple data augmentation operations on the first fundus photography to generate multiple second fundus photographies; generating multiple retinal nerve fiber layer (RNFL) defect assessment results by multiple second models based on the second fundus photographies; obtaining a second assessment result of the eye based on the RNFL defect assessment results; and obtaining an optic nerve assessment result of the eye based on the first assessment result and the second assessment result.