Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.

Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

Abstract: An electronic structure includes a packaging structure, a circuit pattern structure, an underfill and a protrusion structure. The circuit pattern structure is disposed over the packaging structure. A gap is between the circuit pattern structure and the packaging structure. The underfill is disposed in the gap. The protrusion structure is disposed in the gap, and is configured to facilitate the distributing of the underfill in the gap.

Abstract: A power-adjusting method for uplink transmission is provided. The power-adjusting method is applied to user equipment (UE). In response to the UE transmitting a first packet carrying a specific message to a network node, the power-adjusting method includes the UE increasing the transmission power to transmit the first packet.

Abstract: The present disclosure provides binding proteins, such as antibodies and antigen-binding fragments, which specifically bind to human CD200R1 receptor protein (hu-CD200R1) and are capable of decreasing, inhibiting, and/or fully-blocking immune regulatory effects mediated by hu-CD200R1. The present disclosure also provides methods of using the antibodies (and compositions thereof) to treat diseases and conditions responsive to decreasing, inhibiting and/or blocking immune regulatory function or activity mediated by CD200 binding to CD200R1.

Abstract: A high electron mobility transistor (HEMT) device and a method of forming the HEMT device are provided. The HEMT device includes a substrate, a channel layer, a barrier layer, and a gate structure. The substrate has at least one active region. The channel layer is disposed on the at least one active region. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer. The gate structure includes a metal layer and a P-type group III-V semiconductor layer vertically disposed between the metal layer and the barrier layer. The P-type group III-V semiconductor layer includes a lower portion and an upper portion on the lower portion, and the upper portion has a top area greater than a top area of the lower portion.

Abstract: An ultrasonic transducer includes a piezoceramic element with a first surface and a second surface opposite to each other through the piezoceramic element and a lateral surface connecting the first surface and the second surface, an acoustic matching layer with a third surface and a fourth surface opposite to each other through the acoustic matching layer and the third surface connecting with the second surface of the piezoceramic element, a first damping element with a fifth surface and a sixth surface opposite to each other through the first damping element and the sixth surface connecting with the first surface of the piezoceramic element, and a second damping element encapsulating the first damping element and the lateral surface of the piezoceramic element.

Abstract: A solid lithium battery includes a negative electrode layer, a solid electrolyte layer, and a positive electrode layer. The solid electrolyte layer includes a first solid electrolyte. The positive electrode layer includes an active material, a second solid electrolyte, a conductive additive, and an adhesive. A material of the second solid electrolyte includes oxygen-doped sulfide or lithium indium chloride and/or a material of the conductive additive includes graphene.

Abstract: An integrated circuit layout includes a first and a second standard cells abutting along a boundary line. The boundary line and a first active region of the first standard cell include a distance D1. A first gate line on the first active region protrudes from the first active region by a length L1. The boundary line and a second active region of the second standard cell include a distance D2. A second gate line on the second active region protrudes from the second active region by a length L2. Two first dummy gate lines and two second dummy gate lines are disposed at two sides of the first active region and the second active region and are away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.

Abstract: A machining tool thermal compensation system based on an aggregation model includes a calculating module and a processing module. The calculating module executes a first thermal compensation model and a second thermal compensation model. The first thermal compensation model is only related to motor temperature change and the second thermal compensation model is only related to environmental temperature change. The processing module executes an aggregation model based on Kalman filter. The calculating module inputs the motor temperature of a target machining tool at a time point into the first thermal compensation model to generate a first compensation value and inputs the environmental temperature of the target machining tool at this time point into the second thermal compensation model to generate a second compensation value. The processing module executes the aggregation model according to the two compensation values to generate a modified compensation value of this time point.

Abstract: A decoration panel includes a first substrate, a first transparent conductive element, a transparent structure, a second substrate, a second transparent conductive element, and a first cholesteric liquid crystal layer. The first transparent conductive element is disposed on the first substrate. The transparent structure is disposed on the first substrate. The second substrate is disposed opposite to the first substrate. The second transparent conductive element is disposed on the second substrate. The first cholesteric liquid crystal layer is disposed between the first transparent conductive element and the second transparent conductive element. A display apparatus is adapted to render a decoration pattern, and the decoration pattern corresponds to the transparent structure. Moreover, a display apparatus including the decoration panel is also provided.

Abstract: A solid-state battery includes a positive electrode, a negative electrode, and a solid-state electrolyte layer. The solid-state electrolyte layer is disposed between the positive electrode and the negative electrode. The solid-state electrolyte layer includes a sulfide solid-state electrolyte represented by Chemical formula 1, Li6+x+yP1?x?ySixTiyS5?2x?2yBrO2x+2y??[Chemical formula 1] where in Chemical formula 1, 0?x?0.5, 0?y?0.5, and x+y>0.

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

Abstract: A package structure is provided. The package structure includes a substrate, a first electronic component, a first electrical connector, and a protective layer. The first electronic component is over the substrate. The first electrical connector is between the substrate and the first electronic component. The protective layer encapsulates the first electrical connector. The protective layer has a first curved lateral surface concave toward the first electrical connector and recessed with respect to a lateral surface of the first electronic component.

Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.

Abstract: A gas dispenser utilized in a deposition apparatus is provided. The gas dispenser includes a showerhead comprising a plurality of holes, and a mask layer formed on a surface of the showerhead, wherein the holes penetrate through the mask layer. A deposition apparatus using the gas dispenser is also disclosed.

Abstract: The embodiments of the disclosure provide a method for providing a visual content, a host, and a computer readable storage medium. The method includes: providing a reference object at a first location to aim at a first point and accordingly determining a first reference line related to the first point, wherein the first point is associated with an external camera; providing the reference object at a second location to aim at the first point and accordingly determining a second reference line related to the first point; determining a camera position of the external camera based on the first reference line and the second reference line; obtaining a specific image captured by the external camera; and generating a specific visual content via combining the specific image with a virtual scene based on the camera position.

Abstract: A lateral-bipolar junction transistor (BJT) including a semiconductor substrate, an insulator region disposed on the semiconductor substrate, and a well region comprising a well semiconductor of a first conductivity type disposed over the insulator region. An emitter region of a second conductivity type is disposed in the well region, and at least one collector region of a second conductivity type is disposed in the well region. A T shaped, Pi shaped or H shaped gate and gate oxide layer includes a gate portion extending between the emitter region and one or more collector regions, and a base is disposed underneath the gate portion. In other embodiments, a metal oxide semiconductor (MOS) transistor-based circuit similarly employs a compact Pi or H shaped gate and gate oxide layer.

Abstract: The present disclosure relates to a ULBP6 binding protein that inhibits the interaction between ULBP6 and NKG2D, and methods of treating cancer with said ULBP6 binding protein.