Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first alignment pattern having a plurality of first scale patterns arranged in a first direction. The second semiconductor device is mounted over the first semiconductor device and includes a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns.

Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first alignment pattern having a plurality of first scale patterns arranged in a first direction. The second semiconductor device is mounted over the first semiconductor device and includes a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns.

Abstract: Semiconductor dies of a semiconductor die package are directly bonded, and a top metal region may be formed over the semiconductor dies. A plurality of conductive terminals may be formed over the top metal region. The conductive terminals are formed of copper (Cu) or another material that enables low-temperature deposition process techniques, such as electroplating, to be used to form the conductive terminal. In this way, the conductive terminals of the semiconductor die packages described herein may be formed at a relatively low temperature. This reduces the likelihood of thermal deformation of semiconductor dies in the semiconductor die packages. The reduced thermal deformation reduces the likelihood of warpage, breakage, and/or other types of damage to the semiconductor dies of the semiconductor die packages, which may increase performance and/or increase yield of semiconductor die packages.

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.

Abstract: An electronic includes an electronic element, an encapsulation layer surrounding the electronic element, a first circuit structure, a second circuit structure and a connecting structure. The encapsulation layer has a top surface, a bottom surface and an opening, wherein a sidewall of the opening connects the top surface and the bottom surface. The first circuit structure is disposed at the top surface of the encapsulation layer. The second circuit structure is disposed at the bottom surface of the encapsulation layer. The connecting structure is disposed in the opening, wherein the electronic element is electrically connected to the second circuit structure through the first circuit structure and the connecting structure. The connecting structure includes a first sub layer and a second sub layer, the first sub layer is located between the encapsulation layer and the second sub layer, and the first sub layer covers the sidewall of the opening.

Abstract: A mechanism for building decentralized computer applications that execute on a distributed computing system. The present technology works within a web browser, client application, or other software and provides access to decentralized computer applications through the browser. The present technology is non-custodial, wherein a public-private key pair, which represents user identity, is created on a client machine and then directly encrypted by a third-party platform without relying on one centralized computing system.

Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion used for connecting an optical element, a fixed portion, and a driving assembly used for driving the movable portion to move relative to the fixed portion. The movable portion is movable relative to the fixed portion.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: An ionic compound, an absorbent and an absorption device are provided. The ionic compound has a structure represented by Formula (I): ABn, ??Formula (I) wherein A is B is R1, R2, R3, R4, R5, and R6 are independently H, C1-6 alkyl group; and n is 1 or 2.

Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable storage media for monitoring application health via correctable errors. The method includes identifying, by a network device, a network packet associated with an application and detecting an error associated with the network packet. In response to detecting the error, the network device increments a counter associated with the application, determines an application score based at least in part on the counter, and telemeters the application score to a controller. The controller can generate a graphical interface based at least in part on the application score and a timestamp associated with the application score, wherein the graphical interface depicts a trend in correctable errors experienced by the application over a network.

Abstract: A mechanism for building decentralized computer applications that execute on a distributed computing system. The present technology works within a web browser, client application, or other software and provides access to decentralized computer applications through the browser. The present technology is non-custodial, wherein a public-private key pair, which represents user identity, is created on a client machine and then directly encrypted by a third-party platform without relying on one centralized computing system.

Abstract: Some implementations described herein include systems and techniques for fabricating a semiconductor die package that includes a cooling interface region formed in surface of an integrated circuit die. The cooling interface region, which includes a combination of channel regions and pillar structures, may be directly exposed to a fluid above and/or around the semiconductor die package.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

Abstract: At least some embodiments of the present disclosure relate to an electronic package structure. The electronic package structure includes an electronic structure, a wiring structure disposed over the electronic structure, a bonding element connecting the wiring structure and the electronic structure, and a reinforcement element attached to the wiring structure. An elevation difference between a highest point and a lowest point of a surface of the wiring structure facing the electronic structure is less than a height of the bonding element.

Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

Abstract: A rigid wireless charging mouse pad includes a rigid board layer, a double-sided adhesive plate and a coil. The underside of the rigid board layer has a single-ring groove with an inner top groove wall. The double-sided adhesive plate is adhered to the inner top groove wall. The coil has surrounding rings arranged side by side with one another to form a coil module which is stacked on the double-sided adhesive plate in the single-ring groove and adhered by the double-sided adhesive plate to achieve a wireless charging effect by the mouse pad in the condition of having only one single-ring groove on the rigid board layer, so as to achieve the effects of reducing manufacturing difficulty, lowering manufacturing cost, and improving market competitiveness.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.