Abstract: A method of feature substitution for end-to-end image compression, is performed by at least one processor and includes encoding an input image, using a first neural network, to generate an encoded representation, and quantizing the generated encoded representation, using a second neural network, to generate a compressed representation. The first neural network and the second neural network are trained by determining a rate loss, based on a bitrate of the generated compressed representation, and updating the generated encoded representation, based on the determined rate loss.

Abstract: Aspects of the disclosure provide methods and apparatuses for neural network model compression/decompression. In some examples, an apparatus for neural network model decompression includes receiving circuitry and processing circuitry. The processing circuitry decodes, from a bitstream corresponding to a representation of a neural network, at least a syntax element to be applied to multiple blocks in the neural network. Then, the processing circuitry reconstructs, from the bitstream, weight coefficients in the blocks based on the syntax element.

Abstract: The embodiments of this application disclose a method for generating sign language video performed by a computer device. The method includes the following steps: acquiring acquiring listener text, the listener text conforming to grammatical structures of a hearing-friendly person; performing summarization extraction on the listener text to obtain summary text, a text length of the summary text being shorter than a text length of the listener text; converting the summary text into sign language text, the sign language text conforming to grammatical structures of a hearing-impaired person; and generating the sign language video based on the sign language text.

Abstract: A transistor includes a gate electrode, a ferroelectric layer, a channel layer, a gas impermeable layer, a dielectric layer, a source line and a bit line. The ferroelectric layer is disposed on the gate electrode. The channel layer is disposed on the ferroelectric layer. The gas impermeable layer is disposed in between the channel layer and the gate electrode, and in contact with the ferroelectric layer. The dielectric layer is surrounding the ferroelectric layer and the channel layer, and in contact with the gas impermeable layer. The source line and the bit line are embedded in the dielectric layer and connected to the channel layer.

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain

Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.

Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.

Abstract: The present disclosure provides an energy storage system. For example, an energy storage system comprises a chassis and a printed circuit board assembly connected to the chassis and comprising a connecting/disconnecting device configured to connect to a corresponding connecting/disconnecting device on the battery cell for enabling connection of the battery cell to the chassis.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a stacked structure disposed on the substrate. The stacked structure includes multiple alternately stacked insulating layers and gate members. A core structure is disposed in the stacked structure. The core structure includes a memory layer, a channel member, a contact member, and a liner member. The channel member is disposed on the memory layer. The contact member is disposed on the channel member. The liner member surrounds a portion of the core structure. The present disclosure also provides a method for fabricating the semiconductor structure.

Abstract: A conveyor and a conveyor system are provided. The conveyor comprises a lumen assembly and a self-locking mechanism connected to the lumen assembly, wherein the lumen assembly comprises an inner core tube, a recovery sheath movably surrounding the inner core tube, and an outer sheath movably surrounding the recovery sheath; the self-locking mechanism is connected to the recovery sheath; and the outer sheath can move relative to the inner core tube in an axial direction of the conveyor. The self-locking mechanism has a self-locked state and an unlocked state, wherein when the self-locking mechanism is in the unlocked state, the recovery sheath can move relative to the inner core tube in the axial direction of the conveyor; and when the self-locking mechanism is in the self-locked state, the recovery sheath maintains stationary relative to the inner core tube.

Abstract: A device for a cigarette tipping paper anti-adhesion test is disclosed. The device includes the following components: an upper cover (1), a plurality of upper cover semi-cylinders (11) inside the upper cover, having the same radius and arranged in parallel, and a box (2) with a plurality of holes (211) on the box upper surface (21), connected with the inner cavity of the box (2). Each upper cover semi-cylinder has a cross-section with a bow shape. The side wall of the box (2) also has an opening (22). A method for testing anti-adhesion of the cigarette tipping paper using the device is also disclosed. The present device can qualitatively and quantitatively simulate adhesion of tipping paper in various conditions.

Abstract: The present disclosure provides a structure for detecting a crack and a semiconductor device. The structure for detecting a crack includes at least three metal layers, and an interconnection via layer is provided between adjacent metal layers. The structure for detecting a crack further includes multiple detection units. The detection unit includes an intermediate metal segment and at least two metal segment groups. Each of the metal segment groups includes a first metal segment and a second metal segment located in a same metal layer and spaced apart. The intermediate metal segment and each of the metal segment groups are located in different metal layers, and different metal segment groups are located in different metal layers.

Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

Abstract: An intervention guidance device (10) includes a main body portion (100) and a guidance portion (200). The guidance portion (200) has a contracted configuration and an expanded configuration. In the expanded configuration, the guidance portion (200) has a central area (201) and a closed outer edge (202). In the contracted configuration, the outer edge (202) is farther away from the main body portion (100) than the central area (201), and the guidance portion (200) is restorable from the contracted configuration to the expanded configuration. In the intervention guidance device (10), the radial dimension of the guidance portion (200) is larger than the distance between the chordae tendineae, so that an effective access path that does not cross the chordae tendineae can be established, the subsequent implantation of a heart valve prosthesis does not pass through the chordae tendineae, and the success rate of a heart valve prosthesis implantation surgery can be improved.

Abstract: A computer-implemented method according to one embodiment includes updating code segments of source code to include predetermined code pieces. The updated code segments are configured to output information about associated test cases upon the test cases being run. The method further includes running the test cases, and subsequent to a change being made to the source code, determining a prioritized subset of the test cases. The prioritized subset of the test cases is run. A computer program product according to another embodiment includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and/or executable by a computer to cause the computer to perform the foregoing method.

Abstract: The invention relates to method for the efficient expression and purification and application of a recombinant fusion protein of MANNase and homologues thereof and GLP-1. Through genetic recombination technology, soluble proteins are obtained by using high density fermentation of Pichia pastoris to induce secretory expression, followed by isolation and purification by filtration and concentration to obtain high yield of target proteins. The high fermentation expression and simple isolation steps solve the limitations of the current GLP-1 analogs such as low drug yield, high cost and the need for frequent injections. More importantly, the fusion protein has hypoglycemic effect not only by injection, but also by oral administration for hypoglycemia and weight reduction, which has good application value in obese and pre-diabetic patients. It also provides a basis for further research on the mechanism of hypoglycemia and weight loss of mannanase and homologues thereof with GLP-1 recombinant fusion protein.

Abstract: A pruning method of neural network based video coding of a current block of a picture of a video sequence is performed by at least one processor and includes categorizing parameters of a neural network into groups, setting a first index to indicate that a first group of the groups is to be pruned, and a second index to indicate that a second group of the groups is not to be pruned, and transmitting, to a decoder, the set first index and the set second index. Based on the transmitted first index and the transmitted second index, the current block is processed using the parameters of which the first group of the groups is pruned.

Abstract: The present disclosure discloses a mid-span axial force-free connecting device for an earth-anchored cable-stayed bridge and a method for mounting same. The mid-span axial force-free connecting device for an earth-anchored cable-stayed bridge includes an externally sleeved large steel box girder and an internally embedded small steel box girder. A plurality of bearing beams are arranged on the inner periphery of the externally sleeved large steel box girder. Transverse spherical bearings or vertical spherical bearings are arranged on the bearing beams. The internally embedded small steel box girder is fixedly supported in the externally sleeved large steel box girder through a plurality of transverse spherical bearings and vertical spherical bearings. In the same section, the transverse spherical bearings are symmetrically arranged, and the vertical spherical bearings are also symmetrically arranged.

Abstract: Aspects of the disclosure provide methods, apparatuses, and a non-transitory computer-readable storage medium for video encoding and video decoding. An apparatus for video decoding can include processing circuitry. The processing circuitry is configured to decode neural network update information in a coded bitstream for at least one neural network in the video decoder. The at least one neural network is configured with a set of pretrained parameters, and the neural network update information indicates a first modification parameter. The processing circuitry is configured to update the set of pretrained parameters in the at least one neural network in the video decoder based on the first modification parameter. The processing circuitry is configured to decode an encoded image based on the updated at least one neural network.

Abstract: An optical ring resonator that includes a closed loop core, a cladding layer, and one or more bus waveguides. The closed loop core is disposed in the cladding layer and is As2Se3 glass. The one or more bus waveguides are disposed in the cladding layer and are optically coupled to the closed loop core. The closed loop core has a zero-dispersion wavelength within a telecommunication wavelength band. The closed loop core has a plurality of resonant modes, including a zero-dispersion resonant mode corresponding with the zero-dispersion wavelength and a plurality of paired resonant modes. Further, the closed loop core has a phase matching bandwidth extending greater than ±40 nm from the zero-dispersion wavelength.