Abstract: A method and apparatus of for video enhancement based on neural network based loop filtering using meta learning may include receiving reconstructed video data; receiving one or more quality factors associated with the reconstructed video data; determining a neural network based loop filter comprising neural network based loop filter parameters and a plurality of layers, wherein the neural network based loop filter parameters include shared parameters and adaptive parameters; and generating enhanced video data with artefact reduction, based on the one or more quality factors and the reconstructed video data, using a neural network based loop filter, wherein the neural network based loop filter comprises neural network based loop filter parameters that include shared parameters and adaptive parameters.

Abstract: A real-time online analysis device for substance pyrolysis, including: a pyrolyzing system (1), a capturing system (2), a testing system (3) and a controlling system (4) is disclosed. The pyrolyzing system (1), the capturing system (2) and the testing system (3) are connected with the controlling system (4). The capturing system (2) has a cooling cavity (22) and a heating cavity (23) inside. The temperature of the cooling cavity (22) ranges from room temperature to ?200° C., and the temperature of the heating cavity (23) ranges from room temperature to 1000° C. A method for real-time online analysis of substance pyrolysis using the device is also disclosed. The present device can provide real-time online pyrolysis, capturing, separation and analysis of substances at a plurality of temperature points or ranges.

Abstract: An atrioventricular valve clamping device and an atrioventricular valve clamping system are provided in the disclosure. The atrioventricular valve clamping device includes a support member, an occluding member, and a clamping member. A direction of a central axis of the occluding member is regarded as a Z-direction, a direction parallel to a width direction of the clamping member and perpendicular to the Z-direction is regarded as a Y-direction, and a direction perpendicular to the Y-direction and the Z-direction is regarded as an X-direction. The support member has a length in the Z-direction. The occluding member is sleeved on the support member in the Z-direction. The clamping member is disposed outside the occluding member and configured to be unfolded or folded relative to the occluding member. The occluding member is resilient and has a three-dimensional shape.

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

Abstract: The present disclosure relates to an integrated chip including a three-dimensional memory array. The three-dimensional memory array includes a first local line and a second local line that are elongated vertically, a first memory cell extending between the first local line and the second local line, and a second memory cell directly under the first memory cell, extending between the first local line and the second local line, and coupled in parallel with the first memory cell. The first memory cell is coupled to a first word line and the second memory cell is coupled to a second word line. The first word line and the second word line are elongated horizontally. A first global line is disposed at a first height and is elongated horizontally. A first selector extends vertically from the first local line to the first global line.

Abstract: A direct well-tie method for depth-domain logging and seismic data, including: removing null and outlier values from logging velocity data and logging density data to obtain valid logging velocity data and valid logging density data; calculating a logging reflection coefficient; estimating an initial zero-phase depth-domain seismic wavelet from seismic section; making a depth-domain synthetic seismogram; interpolating the depth-domain seismogram at the logging location; performing cross-correlating operation between the depth-domain synthetic seismogram and the interpolated depth-domain seismogram at the logging location; estimating a depth-domain seismic wavelet; updating the depth-domain synthetic seismogram; generating a corresponding depth deviation point set; subjecting elements in the set to interpolation to obtain a depth calibration curve; subjecting the depth calibration curve and depth axis to addition to obtain depth axis; generating a logging depth-seismic depth corresponding relationship and a de

Abstract: A memory device includes a multi-layer stack, a channel layer, a memory material layer and at least three conductive pillars. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The memory material layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The conductive pillars are surrounded by the channel layer and the memory material layer, wherein the at least three conductive pillars are electrically connected to conductive lines respectively.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.

Abstract: Systems, apparatus and methods are provided for electrical mirroring implemented by a storage controller in a non-volatile storage system. In one embodiment, a non-volatile storage system may comprise a plurality of non-volatile storage devices and a storage controller. The storage controller may be configured to perform an electrical mirroring configuration process comprising: determining a system topology of the non-volatile storage system and which targets are in mirrored non-volatile storage devices and setting respective register bits in the storage controller for all targets in all mirrored non-volatile storage devices of the plurality of non-volatile storage devices.

Abstract: A pruning method of neural network based video coding of a current block of a picture of a video sequence is performed by at least one processor and includes categorizing parameters of a neural network into groups, setting a first index to indicate that a first group of the groups is to be pruned, and a second index to indicate that a second group of the groups is not to be pruned, and transmitting, to a decoder, the set first index and the set second index. Based on the transmitted first index and the transmitted second index, the current block is processed using the parameters of which the first group of the groups is pruned.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).

Abstract: A transistor includes a gate electrode, a ferroelectric layer, a channel layer, a gas impermeable layer, a dielectric layer, a source line and a bit line. The ferroelectric layer is disposed on the gate electrode. The channel layer is disposed on the ferroelectric layer. The gas impermeable layer is disposed in between the channel layer and the gate electrode, and in contact with the ferroelectric layer. The dielectric layer is surrounding the ferroelectric layer and the channel layer, and in contact with the gas impermeable layer. The source line and the bit line are embedded in the dielectric layer and connected to the channel layer.

Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain

Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.

Abstract: Disclosed is an injection molding method for a degradable intravascular stent with a flexible mold core structure. The injection molding method includes the following steps: Step 1, winding a metal rod with a flexible metal film, and applying an inward bending stress to the flexible metal film; Step 2, fixing the flexible metal film to the metal rod, and processing a complementary structure of the degradable intravascular stent on the surface of the flexible metal film; Step 3, performing injection molding processing; Step 4, ending the injection molding, removing the mating body of the flexible metal film and the metal rod and the degradable intravascular stent formed on the surface of the flexible metal film by injection molding, performing cooling, separating the metal rod from the flexible metal film, withdrawing the metal rod, and then removing the flexible metal film to obtain a formed degradable intravascular stent.

Abstract: The disclosed embodiments provide a system that facilitates the processing of network data. During operation, the system causes for display a graphical user interface (GUI) for configuring the generation of time-series event data from network packets captured by one or more remote capture agents. Next, the system causes for display, in the GUI, a first set of user-interface elements containing a set of statistics associated with one or more event streams that comprise the time-series event data. The system then causes for display, in the GUI, one or more graphs comprising one or more values from the set of statistics. Finally, the system causes for display, in the GUI, a value of a statistic from the set of statistics based on a position of a cursor over the one or more graphs.

Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

Abstract: Various methods and systems are provided for ultrasound imaging. In one embodiment, a method comprises acquiring, with an ultrasound transducer of a scanning apparatus during an ultrasound scan of a patient, an ultrasound image, detecting, with an artificial intelligence model, a region of interest within the ultrasound image including a possible tumor, acquiring, with the ultrasound transducer, an elastic image of tissue within the region of interest, and displaying, with a display device, the elastic image. In this way, shear wave elastography may be automatically targeted to a region of interest, thereby reducing the processing load for the analysis and enabling a higher elasticity imaging frame rate for three-dimensional ultrasound imaging.

Abstract: Systems, apparatus and methods are provided for multi-drop multi-load NAND interface topology where a number of NAND flash devices share a common data bus with a NAND controller. A method for controlling on-die termination in a non-volatile storage device may comprise receiving a chip enable signal on a chip enable signal line from a controller, receiving an on-die termination (ODT) command on a data bus from the controller while the chip enable signal is on, decoding the on-die termination command and applying termination resistor (RTT) settings in the ODT command to a selected non-volatile storage unit at the non-volatile storage device to enable ODT for the selected non-volatile storage unit.