Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.

Abstract: Embodiments of the present disclosure relate to a method, a device, and a computer program product for data access. The method includes acquiring a priority of a workload associated with an input/output (I/O) instruction of a user, and determining, based on the priority, whether to perform data access to a persistent memory indicated by the I/O instruction by using a central processing unit (CPU). If it is determined not to perform the data access by using the CPU, the data access is performed by using a programmable data moving apparatus. The method according to the embodiments of the present disclosure can avoid that important workloads compete for CPU resources equally with secondary workloads, and alleviate blocking of workloads due to insufficient CPU resources, thereby improving the overall performance of persistent memory access.

Abstract: A method, communication device, and a storage medium for protecting user equipment (UE) discovery messages. The UE discovery messages are protected by sending a first announcement message in response to determining that the first UE is located outside a network coverage range, where the first announcement message includes: a discovery message encrypted based on a discovery key, and LTK identifier information (ID) indicating an LTK, where the discovery key is determined based on the LTK received in response to determining that the first UE is located within the network coverage range, and the LTK ID is used for allowing a second UE to determine a key request to request the discovery key or request to generate an intermediate key of the discovery key.

Abstract: Provided herein is a method of segmenting features from an optical image of a skin comprising steps of receiving an optical image of a skin that contains at least one feature of an object: contrast-enhancing the feature's signals of the optical image from the background signals: segmenting the object in the enhanced optical image, and quantifying the feature from the optical image of the skin.

Abstract: A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.

Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, and a display panel. The array substrate includes an oxide semiconductor layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, and a source-drain electrode metal layer located on a substrate. Wherein the oxide semiconductor layer includes a channel region and conductive regions, the gate insulating layer is respectively overlapped with the conductive regions on both sides of the channel region, and an orthographic projection of a part of the gate electrode corresponding to the oxide semiconductor layer on the substrate falls within a range of an orthographic projection of the channel region on the substrate.

Abstract: A bonding structure, including a first dielectric layer, multiple first conductors, a second dielectric layer, and multiple second conductors, is provided. The first conductors are embedded in the first dielectric layer, the first dielectric layer is bonded with the second dielectric layer, and the second conductors are embedded in the second dielectric layer, wherein the first conductors are bonded with the second conductors, and a bonding interface between the first conductors and the second conductors is a bonding interface containing silver.

Abstract: An information processing method is performed by a first network element, and includes: receiving an operator credential configured by a second network element for a Personal Internet of Things Network Element (PINE); encrypting the operator credential to obtain an encrypted credential; and sending the encrypted credential to the second network element, wherein the encrypted credential is used for a PIN Element with Gateway Capability (PEGC) to perform decryption to obtain the operator credential.

Abstract: An inspection apparatus for inspecting a semiconductor workpiece includes a testing stage, a first seal member, a testing clamp, a second seal member, a semiconductor workpiece, and a transducer. The testing stage has a cavity. The first seal member is disposed in the cavity. The first seal member is attached to a sidewall of the cavity. The testing clamp is movably coupled to the testing stage. The second seal member is attached to the testing clamp. The semiconductor workpiece is held between the testing stage and the testing clamp by the first seal member and the second seal member. The transducer is movably disposed above the testing stage.

Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.

Abstract: A system, method, and computer program product for passively informed mental health risk prediction. The system may include receiving mental health risk input signals from a blood glucometer and other devices. The mental health risk signals may include glucometer data, demographic data, and other data. The glucometer data for the subject may include at least one blood glucose value. The mental health risk input signals are input into a machine learning system. The machine learning system has been previously trained with mental health risk input signals and mental health status data for a plurality of subjects. The machine learning system outputs a prediction of mental health risk for the subject. The machine learning system may comprise a neural network.

Abstract: An audio system may include a microphone configured to sense sound and generate an analog audio signal; an analog-to-digital convertor (ADC) configured to convert the analog audio signal to a digital audio signal having a first bit rate; a motion sensor configured to sense motion associated with the microphone and generate a motion signal representative of the motion associated with the microphone; a motion signal conversion module configured to convert the motion signal to a digital audio noise signal having a second bit rate synchronized with the first bit rate; and a noise suppression module configured to at least partially suppress the digital audio noise signal relative to the digital audio signal to generate a noise-suppressed digital audio signal.

Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an dielectric layer. The first semiconductor package includes a plurality of first semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the first semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of first semiconductor chips, wherein the second semiconductor package includes a plurality of second semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of second semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of first semiconductor chips. The dielectric layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

Abstract: Disclosed is an interference structure, including an interference film layer. The interference film layer includes a plurality of regions, where the plurality of regions includes a transparent region made of transparent material. In a direction perpendicular to the interference film layer, a thickness of at least one region in the plurality of regions is different from a thickness of a region other than the at least one region in the plurality of regions. In other words, in the present disclosure, by including the plurality of regions with different thicknesses in the interference film layer, it is possible to process the incident light into the plurality of beams of interference light corresponding to the incident light, without the need for multiple optical lenses in traditional interference structures. Therefore, the structure of the interference structure in the present disclosure is simple and easy to miniaturize.

Abstract: In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.

Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

Abstract: A self-locking subpackaging bottle comprising a bottle body, a bottle cap and an adapter is provided. The bottle cap comprises a receiving cap and a rotating cap sequentially arranged at a front end of the bottle body; the adapter comprises an adapter cap, a rotating ring and a fixing ring which are coaxially connected, the adapter cap comprises an annular cap, a first bearing arranged on an inner wall of the annular cap and a support ring arranged above the first bearing, the rotating ring is rotatably connected to the interior of the annular cap through the first bearing, and the fixing ring is connected to the interior of the annular cap through the support ring; and an inner wall of the rotating ring meshes with an outer wall of the rotating cap, and an inner wall of the fixing ring meshes with an outer wall of the receiving cap.

Abstract: Methods and systems are presented for providing a framework to securely integrate third-party logic into electronic transaction processing workflow. Third-party programming code that implements different third-party logic may be obtained and stored in a repository. A transaction processing request is received from a third-party server, and an instance of a transaction processing module is instantiated within an operating runtime environment to process a transaction according to a workflow. When the instance of the transaction processing module has reached an interruption point, the instance of the transaction processing module is suspended, and a third-party programming code is executed within an isolated runtime environment. The third-party programming code is configured to provide an output value based on attributes of the transaction. The instance of the transaction processing module then determines whether to authorize or deny the transaction based in part on the output value.

Abstract: The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.