Patents by Inventor Wei Lu

Wei Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250150828
    Abstract: A method, apparatus, and computer-readable medium for improving the reliability of a wireless communication network. The reliability of the wireless communication network is improved by: determining an integrity protection key of a ranging announcement message according to long-term key information sent from a core network, where the integrity protection key is configured to replace a discovery key for integrity protection of the ranging announcement message in a case where the first UE is unable to obtain the discovery key from a mobile communication network.
    Type: Application
    Filed: January 29, 2022
    Publication date: May 8, 2025
    Applicant: Beijing Xiaomi Mobile Software Co., Ltd.
    Inventors: Haoran LIANG, Wei LU
  • Publication number: 20250144009
    Abstract: A topical formulation comprising (a) a therapeutically effective amount of tofacitinib; (b) at least one solvent; and (c) optionally one or more other pharmaceutically acceptable excipients is provided. Also provided is a method for treating and/or preventing autoimmune diseases in a subject administering said topical formulation.
    Type: Application
    Filed: November 15, 2024
    Publication date: May 8, 2025
    Inventors: Chih-Ming Chen, Guang-Wei Lu, Ling-Ying Liaw, Fan-Lun Liu, Shih-Fen Liao, Chou-Hsiung Chen, Yu-Han Kao, Yu-Yin Chen
  • Publication number: 20250138345
    Abstract: An electro-optical device includes a waveguide and a first electrode and a second electrode. The first electrode and the second electrode at first and second sides of the waveguide, wherein the first electrode and the second electrode directly contact and extend beyond the first and second sides of the waveguide respectively.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 1, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuen-Shin Liang, Tsung-Fu Tsai, Szu-Wei Lu, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20250140768
    Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.
    Type: Application
    Filed: December 29, 2024
    Publication date: May 1, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 12285838
    Abstract: A chemical mechanical polishing system includes a platen to hold a polishing pad, a carrier head to hold a substrate against a polishing surface of the polishing pad, and a controller. The polishing pad has a polishing control groove. The carrier is laterally movable by a first actuator across the polishing pad and rotatable by a second actuator. The controller synchronizes lateral oscillation of the carrier head with rotation of the carrier head such that over a plurality of successive oscillations of the carrier head such that when a first angular swath of an edge portion of the substrate is at an azimuthal angular position about an axis of rotation of the carrier head the first angular swath overlies the polishing surface and when a second angular swath of the edge portion of the substrate is at the azimuthal angular position the second angular swath overlies the polishing control groove.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: April 29, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Jimin Zhang, Jianshe Tang, Brian J. Brown, Wei Lu, Priscilla Diep LaRosa
  • Publication number: 20250133800
    Abstract: A semiconductor device includes a MEOL structure and a BEOL structure. The BEOL structure is formed over the MEOL structure and includes a first dielectric layer, a spacer and a conductive portion. The first dielectric layer has a lateral surface and a recess, wherein the recess is recessed with respect to the lateral surface. The spacer is formed the lateral surface and covers an opening of the recess. The conductive portion is formed adjacent to the spacer.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 24, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hwei-Jay CHU, Hsi-Wen TIEN, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Chih-Wei LU, Cheng-Hao CHEN
  • Publication number: 20250125012
    Abstract: A tumor neoantigen prediction method and a tumor neoantigen prediction system are provided. In the method, multiple amino acid sequences in genes of a person to be tested are extracted as multiple test peptides to be compared with multiple human protein sequences in a protein sequence database to find multiple similar peptides that match the human protein sequences. The similar peptides are filtered out from the test peptides and the filtered test peptides are input to multiple trained human leukocyte antigen (HLA) models to obtain multiple ranking results of the test peptides. A weighted sum of rankings of each test peptide in the ranking results is calculated as a score of the test peptide. At least one of the test peptides is selected as a neoantigen adapted for the person to be tested according to the score.
    Type: Application
    Filed: November 7, 2023
    Publication date: April 17, 2025
    Applicant: Acer Incorporated
    Inventors: Chi-Wei Lu, Ying-Ja Chen, Li-Tzu Yeh, Tao-Chuan Shih, Cing-Han Yang, Tun-Wen Pai
  • Publication number: 20250126083
    Abstract: Implementations can receive user input during a dialog session between a user and an automated assistant at a client device of the user and via an automated assistant platform, and in response to determining that the user input requires a user interaction with a non-assistant platform: store a state of the dialog session between the user and the automated assistant, transmit a request to initiate the user interaction to the non-assistant platform that causes an additional client device of the user to render a prompt for completing the user interaction, and receive a token associated with the user interaction from the non-assistant platform. In response to receiving the token associated with the user interaction, implementations can cause the dialog session between the user and the automated assistant to be resumed based on the stored state of the dialog session and based on the token associated with the user interaction.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Inventors: Wei Lu, Wangmuge Qin, Suleyman Yurekli, Jeffrey Caesar, Mikhail Turilin
  • Publication number: 20250125251
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, strained layers, source/drain contact patterns, a gate contact via, and source/drain contact vias. The gate structure is disposed over the semiconductor substrate. The strained layers are disposed aside the gate structure. The source/drain contact patterns are disposed on and electrically connected to the strained layers. Top surfaces of the source/drain contact patterns are coplanar with a top surface of the gate structure. The gate contact via is disposed on and electrically connected to the gate structure. The source/drain contact vias are disposed on and electrically connected to the source/drain contact patterns.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Ling Su, Chia-Wei Su, Tsu-Chun Kuo, Wei-Hao Liao, Hsin-Ping Chen, Yung-Hsu Wu, Ming-Han Lee, Shin-Yi Yang, Chih Wei LU, Hsi-Wen Tien, Meng-Pei Lu
  • Publication number: 20250125189
    Abstract: A method for manufacturing an interconnect structure includes: forming a first dielectric layer; forming a mask; patterning the first dielectric layer through the mask to form a trench, an inner surface of the trench having two first portions opposite to each other along an X direction, two second portions opposite to each other along a Y direction, and a bottom portion; forming a second dielectric layer over the mask and the patterned first dielectric layer, and along an inner surface of the trench; etching the second dielectric layer by directing an etchant in a predetermined direction such that a first part of the second dielectric layer on the two first portions and the bottom portion is removed, and a second part of the second dielectric layer on the second portions of the trench remains and is formed into two reinforcing spacers; and forming a trench-filling element.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 17, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Chih-Wei LU, Hwei-Jay CHU, Yu-Teng DAI, Hsin-Chieh YAO, Yung-Hsu WU, Li-Ling SU, Chia-Wei SU, Hsin-Ping CHEN
  • Patent number: 12278162
    Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsun Wang, Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 12275715
    Abstract: The invention relates to inhibitors of mutant isocitrate dehydrogenase (mt-IDH) proteins with neomorphic activity useful in the treatment of cell-proliferation disorders and cancers, having the Formula: where A, U, W1, W2, W3, R1-R6, and R9 are described herein.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: April 15, 2025
    Assignee: FORMA Therapeutics, Inc.
    Inventors: Jian Lin, Anna Ericsson, Ann-Marie Campbell, Gary Gustafson, Zhongguo Wang, R. Bruce Diebold, Susan Ashwell, David R. Lancia, Jr., Justin Andrew Caravella, Wei Lu
  • Publication number: 20250115342
    Abstract: The present disclosure provides an underwater helicopter with cycloidal rim vector propulsion. The underwater helicopter includes a disc-shaped underwater helicopter hull, a rim driving mechanism, paddles and rotation adjusting mechanisms. The rim driving mechanism is annular, and the diameter size of the rim driving mechanism is matched with the circumference size of the disc-shaped underwater helicopter hull. The rim driving mechanism is fixedly installed in a cavity in the circumference of the disc-shaped underwater helicopter hull. The rotation adjusting mechanisms are uniformly and fixedly installed on the outer side of the rim driving mechanism. The paddle is fixedly connected with the rotation adjusting mechanism.
    Type: Application
    Filed: February 29, 2024
    Publication date: April 10, 2025
    Inventors: Chen-Wei CHEN, Jialin LU, Wei LU, Tianjiang ZHENG, Min-Chiang CHAO
  • Publication number: 20250114908
    Abstract: A system may include a gimbal defining a plurality of pockets, where each pocket may include a first portion and a second portion that extends between the first portion and a base of the pocket. The second portion may have a greater diameter than the first portion. The system may include a plurality of conditioning disks, where each conditioning disk is seated within the first portion of a respective pocket. The system may include a plurality of gaskets, where each gasket is seated within the second portion of a respective pocket. The system may include a plurality o-rings, each o-ring disposed between a peripheral edge of one of the plurality of conditioning disks and a lateral wall of one of the plurality of pockets. The system may include a plurality of shoulder screws for coupling the gimbal with one of the plurality of gaskets and a conditioning disk.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 10, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Nai-Chieh Huang, Akshay Aravindan, Shih-Haur Shen, Jianshe Tang, Jay Gurusamy, Chen-Wei Chang, Chih-Han Yang, Wei Lu
  • Publication number: 20250118656
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a first conductive line, a first conductive via, a second conductive line, and a first barrier layer. The first conductive line is disposed on the substrate. The first conductive via is disposed on the first conductive line. The second conductive line is disposed on the first conductive line. The first barrier layer is disposed between the first conductive via and the second conductive line.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Inventors: HWEI-JAY CHU, HSI-WEN TIEN, WEI-HAO LIAO, YU-TENG DAI, HSIN-CHIEH YAO, CHENG-HAO CHEN, CHIH WEI LU
  • Patent number: 12272568
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai
  • Patent number: 12268139
    Abstract: The present disclosure discloses a water recycling type greenhouse, including a greenhouse body; a water collection device is arranged in the greenhouse body; the water collection device is provided with an air inlet and an air outlet; a condensation portion and a reheating portion are arranged in the water collection device; and the water recycling type greenhouse further includes an energy supply system. Air in the greenhouse body can be poured into the water collection device from the air inlet, flow through the condensation portion and the reheating portion in sequence, and finally be discharged into the greenhouse body again from the air outlet. When the heated air is discharged into the greenhouse body again, a decrease of the temperature of the greenhouse is not likely to occur, and normal growth of plants is not easily affected.
    Type: Grant
    Filed: March 21, 2023
    Date of Patent: April 8, 2025
    Assignee: Institute of Urban Agriculture, Chinese Academy of Agricultural Sciences
    Inventors: Wanlai Zhou, Qichang Yang, Zhiyong Qi, Wei Lu, Bo Zhou, Nan Wang
  • Publication number: 20250113604
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes forming first channel structures, second channel structures, and third channel structures. The method also includes forming gate dielectric layers surrounding the first channel structures, the second channel structures, and the third channel structures and forming dipole layers over the gate dielectric layers. The method also includes forming a dummy material in a first space between the first and the second channel structures and in a second space between the second and the third channel structures and removing first portions of the dummy material. The method also includes implanting first dopants in the dummy material in the first space and removing second portions of the dummy material in the first space and the second space. The method also includes removing the dipole layers in the top device region and completely removing the dummy material.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kenichi SANO, Chia-Yun CHENG, Yu-Wei LU, I-Ming CHANG, Pinyen LIN
  • Publication number: 20250112087
    Abstract: A method for fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; etching a trench opening in the second dielectric layer, wherein the trench opening exposes a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer, the first sidewall of the second dielectric layer extends substantially along a first direction, and the second sidewall of the second dielectric layer extends substantially along a second direction different from the first direction in a top view; forming a via etch stop layer on the first sidewall of the second dielectric layer, wherein the second sidewall of the second dielectric layer is free from coverage by the via etch stop layer; forming a conductive line in the trench opening; and forming a conductive via over the conductive line.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 3, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hwei-Jay CHU, Hsi-Wen TIEN, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Tzu-Hui WEI, Chih Wei LU, Chan-Yu LIAO, Li-Ling SU, Chia-Wei SU, Yung-Hsu WU, Hsin-Ping CHEN
  • Patent number: D1070094
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: April 8, 2025
    Assignee: HUIZHOU FORYOU MEDICAL DEVICES CO., LTD.
    Inventors: Xiaodong Liu, Wei Lu, Mingming Ma