Patents by Inventor Wei Lu

Wei Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210059423
    Abstract: An electric adjustment device for sofa headrest includes a first fixing member, a second fixing member, and a drive device having an output end that linearly reciprocates. One end of the second fixing member is pivotally connected to the first fixing member, and the drive device is pivotally connected to the first fixing member and arranged flush with the first fixing member. A sliding direction of the output end is perpendicular to a pivotal axis about which the second fixing member is pivotable to the first fixing member. Specifically, the second fixing member is extended downward to form a fixed end for fixing to a backrest support frame. The electric adjustment device is installed in the headrest support frame instead of the backrest support frame, so that other functional parts are installed inside internal space of the backrest support frame which improves the function of the sofa.
    Type: Application
    Filed: November 1, 2019
    Publication date: March 4, 2021
    Inventor: Wei Lu
  • Publication number: 20210066211
    Abstract: A package structure includes a circuit substrate and a semiconductor package. The semiconductor package is disposed on the circuit substrate, and includes a plurality of semiconductor dies, an insulating encapsulant and a connection structure. The insulating encapsulant comprises a first portion and a second portion protruding from the first portion, the first portion is encapsulating the plurality of semiconductor dies and has a planar first surface, and the second portion has a planar second surface located at a different level than the planar first surface. The connection structure is located over the first portion of the insulating encapsulant on the planar first surface, and located on the plurality of semiconductor dies, wherein the connection structure is electrically connected to the plurality of semiconductor dies and the circuit substrate.
    Type: Application
    Filed: May 4, 2020
    Publication date: March 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, Li-Chung Kuo, Szu-Wei Lu, Ying-Ching Shih
  • Publication number: 20210066688
    Abstract: The present disclosure relates to an energy storage assembly for a construction machine, such as a tracked construction machine, comprising at least a first and a second energy storage device such as a first and a second battery device, the energy storage devices each being configured to power a working equipment and/or locomotion of the construction machine, a rack mountable to the construction machine, the rack being configured to support the first and second energy storage devices, such as vertically above each other, and a first damping device for damping vertical shocks acting on the first energy storage device and a separate second damping device for damping vertical shocks acting on the second energy storage device.
    Type: Application
    Filed: July 29, 2020
    Publication date: March 4, 2021
    Inventors: Weilin Wu, Wen Cai, Wei Lu
  • Patent number: 10936875
    Abstract: The present disclosure provides a method and apparatus for detecting significance of promotional information, a device and a computer storage medium. The method comprises: extracting each frame of image in a video segment, taking the image as input of a significance detecting module, and obtaining an output result of the significance detecting model; based on the output result, determining a significance score of promotional information corresponding to said each frame of image; obtaining the significance of promotional information corresponding to the video segment, based on the significance score of promotional information corresponding to each frame of image.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 2, 2021
    Assignee: BAIDU ONLINE NETWORK TECHNOLOGY (BEIJING) CO., LTD.
    Inventors: Yi Yang, Jiacheng Guo, Shanyu Wang, Lin Liu, Zhen Chen, Jianguo Wang, Cunchao Wei, Wei Lu, Yueran Dang
  • Patent number: 10932704
    Abstract: A device for measuring brain oxygen level of a subject, including a probe (210) and a detecting means (220), which are respectively coupled to a processor (230). According to the example, the probe (210) includes three light sources (215a, 215b, 215c) that simultaneously emit the first, second, and third NIR wavelengths across the brain of the subject. The first NIR wavelength is the isosbestic wavelength for oxy-hemoglobin (HbO2) and deoxy-hemoglobin (Hb), the second NIR wavelength is shorter than the first NIR wavelength, and the third NIR wavelength is longer than the first NIR wavelength. The detecting means (220) includes a first, second and third detectors (221, 222, 223) for respectively detecting the NIR intensities of the first, second and third NIR wavelengths traveled across the brain. The processor (230) is configured to determine blood oxygen level based on the measured NIR intensities of the first, second and third NIR wavelengths by use of build-in algorithm derived from Beer-Lambert Law.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: March 2, 2021
    Assignee: MACKAY MEMORIAL HOSPITAL
    Inventors: Wen-Han Chang, Chih-Wei Lu
  • Patent number: 10937652
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee
  • Patent number: 10934552
    Abstract: The disclosure herein relates to construction and application of engineering bacteria capable of secreting and expressing diacetylchitobiose deacetylase, and belongs to the technical field of fermentation engineering. Firstly, recombinant B. subtilis capable of heterologously secreting and expressing a diacetylchitobiose deacetylase gene is constructed, and a signal peptide fragment yncM is added into the recombinant vector for the first time. The signal peptide can secrete the target protein diacetylchitobiose deacetylase outside the cells of the recombinant B. subtilis, and a mutant of the 5?-end untranslated region is acquired, thereby significantly increasing the expression level of the target protein, and greatly simplifying the subsequent enzyme separation and purification steps. When the acquired diacetylchitobiose deacetylase is fermented and cultured in a fermentation medium for 50-60 h, the enzyme activity reaches a maximum of 1,548.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: March 2, 2021
    Assignees: Jiangnan University, SHANDONG RUNDE BIOTECHNOLOGY CO., LTD
    Inventors: Long Liu, Jian Chen, Guocheng Du, Xueqin Lv, Jianghua Li, Zhu Jiang, Wei Lu, Hongzhi Zhang, Jianxing Lu, Changfeng Liu
  • Publication number: 20210057334
    Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a metal feature in a first dielectric layer, an etch stop layer (ESL) over the metal feature, a second dielectric layer over the ESL, a third dielectric layer over the second dielectric layer, a patterned hard mask having a trench. The method further includes forming a via opening through the trench in the patterned hard mask, the second dielectric layer, the third dielectric layer, and the ESL to expose the metal feature, depositing a metal layer in the trench and the via opening to form a metal line and a metal contact via, respectively, and over the workpiece, removing the patterned hard mask between the metal line and the metal contact via, and depositing a fourth dielectric layer between the metal line and the metal contact via.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Hsin-Chieh Yao, Chih Wei Lu, Chung-Ju Lee
  • Publication number: 20210057384
    Abstract: Semiconductor packages and methods of forming the same are provided. One of the semiconductor packages includes a first semiconductor die, an adhesive layer, a second semiconductor die and an underfill. The first semiconductor die includes a first surface, and the first surface includes a central region and a peripheral region surrounding the central region. The adhesive layer is adhered to the peripheral region and exposes the central region. The second semiconductor die is stacked over the first surface of the first semiconductor die. The underfill is disposed between the first semiconductor die and the second semiconductor die.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Fu Kao, Chih-Yuan Chien, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20210055804
    Abstract: An interaction method, device and equipment for operable object.
    Type: Application
    Filed: May 9, 2019
    Publication date: February 25, 2021
    Inventors: Guibin CHEN, Chi FANG, Wei LU, Huayun MIAO, Yonghao LUO, Yi LI, Yumeng LI
  • Publication number: 20210057383
    Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.
    Type: Application
    Filed: November 10, 2020
    Publication date: February 25, 2021
    Inventors: Szu-Wei Lu, Ying-Da Wang, Li-Chung Kuo, Jing-Cheng Lin
  • Publication number: 20210057297
    Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes an interposer, a first semiconductor die and a second semiconductor die over the interposer. The method for forming a package structure also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component. The method for forming a package structure further includes forming an underfill layer between the dam structure and the package component, and removing the dam structure after the underfill layer is formed.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Chih-Hao CHEN, Chih-Chien PAN, Li-Hui CHENG, Chin-Fu KAO, Szu-Wei LU
  • Publication number: 20210057343
    Abstract: A package structure is provided. The package structure includes a first redistribution structure and an interposer over the first redistribution structure. The package structure also includes a molding compound layer surrounding the interposer, and a second redistribution structure over the interposer. The molding compound layer is between the first redistribution structure and the second redistribution structure. The package structure further includes a first semiconductor die and a second semiconductor die over the second redistribution structure.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Chin-Chuan CHANG, Szu-Wei LU
  • Patent number: 10925547
    Abstract: A system for monitoring a physiological condition of a user includes a first measuring apparatus for personal use, a second measuring apparatus for use by medical professionals, and a server. The first measuring apparatus measures a first physiological parameter of the user. The second measuring apparatus measures a second physiological parameter of the user. The server receives the first and second physiological parameters measured by the first and second measuring apparatuses. The measured values of the first and second physiological parameters are associated with a disease condition, a health condition, a nutrient intake condition, a fitness condition or an exercise condition of the user.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: February 23, 2021
    Assignee: Bionime Corporation
    Inventors: Ming-Luen Chang, Cheng-Wei Lu, Kuo-Chih Ho, Kai-Fa Chang, Yung-Feng Lai, Jui-Chi Weng
  • Patent number: 10925522
    Abstract: A method for dynamic analysis of a physiological parameter of a user includes: generating a first event label corresponding to a first measurement value of the physiological parameter measured at a first time point; generating a second event label corresponding to a second measurement value of the physiological parameter measured at a second time point; calculating a time difference between the first and second time points; calculating a measurement value difference between the first and second measurement values when a time difference between the first and second time points is smaller than a time length threshold; and providing an analysis outcome based on the first and second event labels and the measurement value difference.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: February 23, 2021
    Assignee: Bionime Corporation
    Inventors: Ming-Luen Chang, Cheng-Wei Lu
  • Publication number: 20210051148
    Abstract: Synchronization of access controls between computing devices is provided. The system receives a request from a first device. The system performs a session handover to a second device responsive to determining an incompatibility. The system modifies a parameter in an access control database. The system receives a request from a third device. The system provides the digital component to the third device.
    Type: Application
    Filed: February 19, 2019
    Publication date: February 18, 2021
    Inventors: Stavan Parikh, Wei Lu, Tarun Jain, Anshul Gupta, Srishti Srivastava
  • Patent number: 10923438
    Abstract: A package structure and method for forming the same are provided. The method includes forming a through substrate via structure in a substrate, and forming a first trench in the substrate. The method includes stacking a first stacked die package structure over the substrate using a plurality of first bonding structures. The first bonding structures are between the substrate and the first stacked die package structure, and a there is plurality of cavities between two adjacent first bonding structures. The method also includes forming an underfill layer over the first stacked die package structure and in the cavities, and the underfill layer is formed in a portion of the first trench. The method further includes forming a package layer over the underfill layer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, I-Ting Huang, Shih-Ting Lin, Szu-Wei Lu
  • Publication number: 20210043569
    Abstract: A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a second constituent polymer is formed over the first layer. The first constituent polymer is selectively removed from the copolymer layer. A first region of the first layer corresponding to the selectively removed first constituent polymer is etched. The etching leaves a second region of the first layer underlying the second constituent polymer unetched. A metallization process is performed on the etched substrate, and the first layer is removed from the second region to form an air gap. The method may further comprise depositing a dielectric material within the etched first region.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Inventors: Chih Wei Lu, Chung-Ju Lee, Tien-I Bao
  • Publication number: 20210038685
    Abstract: Disclosed is a protein comprising no more than three human autoantigenic proteins, wherein a first human autoantigenic protein comprises a truncated myelin oligodendrocyte glycoprotein (MOG) amino acid sequence, a second human autoantigenic protein comprises a myelin basic protein (MBP) amino acid sequence, and a third human autoantigenic protein comprises a truncated proteolipid protein (PLP) amino acid sequence. Also disclosed are related nucleic acids, pharmaceutical compositions, methods of treating a demyelinating disease, and methods of producing the proteins.
    Type: Application
    Filed: July 21, 2020
    Publication date: February 11, 2021
    Inventors: Michael J. Lenardo, Jian Li, Lixin Zheng, Jae W. Lee, Wei Lu
  • Patent number: 10916488
    Abstract: Semiconductor packages are provided. One of the semiconductor package includes a semiconductor die, a thermal conductive pattern, an encapsulant and a thermal conductive layer. The thermal conductive pattern is disposed aside the semiconductor die. The encapsulant encapsulates the semiconductor die and the thermal conductive pattern. The thermal conductive layer covers a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Szu-Wei Lu