Patents by Inventor Wei Lu

Wei Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SELF-ALIGNED INTERCONNECT STRUCTURE
    Publication number: 20230369281
    Abstract: The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao
  • PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230369370
    Abstract: A package structure includes an optical die, an optical die, a supporting structure, and a lens structure. The optical die includes a photonic region. The optical die is disposed on and electrically coupled to the optical die. The supporting structure is disposed on the optical die, where the electric die is disposed between the supporting structure and the optical die. The lens structure is disposed on the supporting structure and optically coupled to the photonic region of the optical die, where the supporting structure is disposed between the lens structure and the electric die.
    Type: Application
    Filed: May 13, 2022
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu, Wei-An Tsao, Che-Yuan Yang, Chien-Ting Chen, Chih-Chieh Hung
  • INTEGRATED CHIP WITH INTER-WIRE CAVITIES
    Publication number: 20230369231
    Abstract: The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Yen Huang, Chia-Tien Wu
  • Structure and Method for a Low-K Dielectric With Pillar-Type Air-Gaps
    Publication number: 20230369228
    Abstract: A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a second constituent polymer is formed over the first layer. The first constituent polymer is selectively removed from the copolymer layer. A first region of the first layer corresponding to the selectively removed first constituent polymer is etched. The etching leaves a second region of the first layer underlying the second constituent polymer unetched. A metallization process is performed on the etched substrate, and the first layer is removed from the second region to form an air gap. The method may further comprise depositing a dielectric material within the etched first region.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Inventors: Chih Wei Lu, Chung-Ju Lee, Tien-I Bao
  • MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE USING JIG
    Publication number: 20230369283
    Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING
    Publication number: 20230369099
    Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer over a substrate, a metal layer over the first dielectric layer, a first conductive structure passing through the metal layer and the first dielectric layer, a second conductive structure passing through the metal layer and the first dielectric layer, and a third conductive structure coupling the first conductive structure to the second conductive structure, and overlying a first portion of the metal layer between the first conductive structure and the second conductive structure, wherein an interface exists between the metal layer and at least one of the first conductive structure or the second conductive structure.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Hsi-Wen TIEN, Wei-Hao LIAO, Pin-Ren DAI, Chih Wei LU, Chung-Ju LEE
  • SELF-ASSEMBLED DIELECTRIC ON METAL RIE LINES TO INCREASE RELIABILITY
    Publication number: 20230369108
    Abstract: Some embodiments of the present disclosure relate to a semiconductor structure including a first conductive wire disposed over a substrate. A dielectric liner is arranged along sidewalls and an upper surface of the first conductive wire and is laterally surrounded by a first dielectric layer. The dielectric liner and the first dielectric layer are different materials. A conductive via is disposed within a second dielectric layer over the first conductive wire. The conductive via has a first lower surface disposed over the first dielectric layer and a second lower surface below the first lower surface and over the first conductive wire.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Yu-Teng Dai, Hsin-Chieh Yao, Chung-Ju Lee
  • Package structure with underfill
    Patent number: 11817425
    Abstract: A package structure is provided. The package structure includes a substrate and a stack of semiconductor dies over the substrate. The package structure also includes an underfill element covering sidewalls of the semiconductor dies. The package structure further includes a protective film attached to the substrate and laterally surrounding the underfill element and the semiconductor dies. The underfill element separates the protective film from the semiconductor dies.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hsuan Tsai, Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu
  • Integrated circuit package and method
    Patent number: 11817410
    Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chih Chiou, Chen-Hua Yu, Shih Ting Lin, Szu-Wei Lu
  • Redundancy schemes for repairing column defects
    Patent number: 11815995
    Abstract: A memory device is provided that includes a memory array including a first array, a first redundant array that is local to the first array, a second array, and a second redundant array that is local to the second array, a cache array including a first cache, a first redundant cache that is local to the first cache, a second cache and a second redundant cache that is local to the second cache, and circuits comprising logic to execute operations. The operations include, responsive to an identification of a defective column in the first array, performing a local defect write repair and responsive to an identification of another defective column in the first array and a determination that the first redundant array is fully utilized, performing a global defect write repair by transferring data into the second redundant array through the first cache and the second redundant cache.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: November 14, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Che-Wei Liang, Shuo-Nan Hung, Hung-Wei Lu, Ming-Cheng Tu
  • Dendrite-Free Lithium Metal Battery by Deformation-Induced Potential Shielding
    Publication number: 20230361362
    Abstract: Disclosed are a system and methods for preventing dendrite growth in an electrochemical cell through the use of a protective layer. The electrochemical cell may comprise an anode, a cathode, an electrolyte, and a protective layer, wherein the protective layer is capable of producing a voltage. The voltage produced can selectively shield metal ions from certain regions of the protective layer. This shielding can result in a more uniform flux of metal ions being transferred across the electrode-electrolyte interface in subsequent electrodeposition and electrodissolution processes. As a result, an electrode with such a protective layer can exhibit improved performance and durability, including markedly lower overpotentials and largely improved metal (e.g., lithium) retention.
    Type: Application
    Filed: July 17, 2023
    Publication date: November 9, 2023
    Inventor: Wei Lu
  • PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230361052
    Abstract: A package structure includes a redistribution circuit structure, a wiring substrate, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has dielectric layers. The wiring substrate is disposed on the redistribution circuit structure. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure includes reinforcement pattern layers and reinforcement vias. The reinforcement pattern layers and the dielectric layers are stacked alternately. The reinforcement vias penetrate through the dielectric layers to connect the reinforcement pattern layers. At least one of the reinforcement pattern layers is embedded in the insulating encapsulation. The reinforcement structure is electrically floating.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu, Chen-Hsuan Tsai, I-Ting Huang
  • SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20230363080
    Abstract: A semiconductor package assembly includes a circuit board, a heat dissipating element and a semiconductor device. The circuit board includes a conductive pattern. The heat dissipating element is located on the circuit board, where the heat dissipating element is connected to the conductive pattern. The semiconductor device is located on the circuit board and next to the heat dissipating element, where the semiconductor device is thermally connected to the heat dissipating element through the conductive pattern.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Ting Chen, Cheng-Wei Lu, Kuang-Hua Wang
  • CLAMPING DEVICE, ELECTRONIC DEVICE AND REMOTE CONTROL METHOD OF ELECTRONIC DEVICE
    Publication number: 20230362488
    Abstract: A clamping device, an electronic device, and a remote control method of the electronic device. The clamping device includes a clamping unit, a first communication unit, and a control unit. The clamping unit is suitable for clamping the electronic device. The first communication unit is suitable for pairing with a second communication unit of the electronic device. The control unit is coupled to the clamping unit and the first communication unit. When the clamping unit is switched from an off mode to an on mode, the control unit controls the first communication unit to pair with the second communication unit and sends a screen-off command to the second communication unit via the first communication unit after the pairing is completed. When the clamping unit is in a clamping mode, the control unit sends an application open command to the second communication unit via the first communication unit.
    Type: Application
    Filed: October 20, 2022
    Publication date: November 9, 2023
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Yea-Chin Yeh, Chi-Hwa Ho, Yi-Teng Tsai, Chun-Wei Lu
  • INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME
    Publication number: 20230361029
    Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a second conductive feature, a third conductive feature, and a dielectric fill. The first conductive feature is disposed in the dielectric layer. The second conductive feature is disposed over the first conductive feature. The second conductive feature includes a first conductive layer disposed over the first conductive feature, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. The first conductive layer, the second conductive layer and the third conductive layer have substantially the same width. The third conductive feature is disposed over the dielectric layer. The dielectric fill is disposed over the dielectric layer between the second conductive feature and the third conductive feature.
    Type: Application
    Filed: July 20, 2023
    Publication date: November 9, 2023
    Inventors: Wei-Hao Liao, Hsi-Wen Tien, Yu-Teng Dai, Chih Wei Lu, Hsin-Chieh Yao, Chung-Ju Lee
  • METHOD OF FABRICATING PACKAGE STRUCTURE
    Publication number: 20230360995
    Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Integrated circuit package and method of forming same
    Patent number: 11810831
    Abstract: An integrated circuit package and a method of forming the same are provided. A method includes stacking a plurality of integrated circuit dies on a wafer to form a die stack. A bonding process is performed on the die stack. The bonding process mechanically and electrically connects adjacent integrated circuit dies of the die stack to each other. A dam structure is formed over the wafer. The dam structure surrounds the die stack. A first encapsulant is formed over the wafer and between the die stack and the dam structure. The first encapsulant fills gaps between the adjacent integrated circuit dies of the die stack. A second encapsulant is formed over the wafer. The second encapsulant surrounds the die stack, the first encapsulant and the dam structure.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu
  • Mobility management processing method and apparatus
    Patent number: 11812503
    Abstract: A mobility management processing method includes: receiving, by an SMF network element, a data notification message that includes a PDU session identifier and that is sent by a UPF network element, and determining, based on the PDU session identifier, a session and SSC mode corresponding to the PDU session identifier and/or a service area of the UPF network element, where the UPF network element is a network element that establishes a PDU session corresponding to the PDU session identifier; determining a paging area based on the SSC mode and/or the service area of the UPF network element; and sending a first message including the paging area to an AMF network element, where the first message is used to trigger the AMF network element to page, in the paging area, a terminal that establishes the PDU session by using the UPF network element.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: November 7, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Wei Lu, Weisheng Jin
  • REDUNDANCY SCHEMES FOR REPAIRING COLUMN DEFECTS
    Publication number: 20230350749
    Abstract: A memory device is provided that includes a memory array including a first array, a first redundant array that is local to the first array, a second array, and a second redundant array that is local to the second array, a cache array including a first cache, a first redundant cache that is local to the first cache, a second cache and a second redundant cache that is local to the second cache, and circuits comprising logic to execute operations. The operations include, responsive to an identification of a defective column in the first array, performing a local defect write repair and responsive to an identification of another defective column in the first array and a determination that the first redundant array is fully utilized, performing a global defect write repair by transferring data into the second redundant array through the first cache and the second redundant cache.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Che-Wei LIANG, Shuo-Nan HUNG, Hung-Wei LU, Ming-Cheng TU
  • Amplifier input pair protection
    Patent number: 11804255
    Abstract: A memory device includes a voltage generator configured to generate a reference voltage for transmission to at least one component of the memory device. The voltage generator includes a first input to receive a first signal having a first voltage value. The voltage generator also includes a second input to receive a second signal having a second voltage value. The voltage generator further includes a first circuit configured to generate third voltage and a second circuit coupled to the first circuit to receive the third voltage value, wherein the second circuit receives the first signal and the second signal and is configured to utilize the third voltage value to facilitate comparison of the first voltage value and the second voltage value to generate an output voltage.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: October 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Zhi Qi Huang, Wei Lu Chu