Abstract: Embodiments herein relate to protection of a standby amplifier of a memory device. Specifically, an input voltage of the standby amplifier may be reduced to decrease an occurrence of damage to the standby amplifier or components thereof. In some embodiments, the input voltage may be reduced using a voltage divider that provides the reduced input voltage to the standby amplifier during a power up operation. Upon completion of the power up operation, the input voltage of the standby amplifier may return to an operating voltage. The reduced input voltage may reduce the occurrence of damage to the standby amplifier by maintaining a gate to drain voltage of one or more transistors of the standby amplifier below a maximum.

Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.

Abstract: The technology of this application relates to a high electron mobility transistor including a GaN substrate layer, a barrier layer, a circuit layer, and a field plate that are sequentially stacked. The GaN substrate layer includes a main body layer and a channel layer that are stacked, the channel layer is adjacent to the barrier layer, the circuit layer includes a source, a drain, and a dielectric layer, the dielectric layer is disposed between the source and the drain, the field plate is disposed on a side that is of the dielectric layer and that is away from the barrier layer, an orthographic projection of the field plate on the channel layer is a field plate projection, the channel layer includes a modulation region and a non-modulation region, the non-modulation region surrounds the modulation region, the modulation region and the field plate projection at least partially overlap.

Abstract: Disclosed is a short-wave infrared spectrum detector, including: a photosensitive chip, including a plurality of detection pixels; a substrate; and a wavelength division component array, including a plurality of wavelength division pixels, each of the plurality of wavelength division pixels corresponding to a narrowband transmission spectrum, wherein the photosensitive chip and the wavelength division component array are monolithically integrated on both sides of the substrate, and an orthographic projection of each of the plurality of wavelength division pixels on the substrate covers an orthographic projection of at least one detection pixel on the substrate. The wavelength division structure and the photosensitive chip are integrated, so that each pixel has the ability of frequency-selective light spectrum detection, and a short-wave infrared spectrum detector integrated with wavelength division and detection is formed, realizing the miniaturization of the short-wave infrared spectral detection system.

Abstract: A flip-chip bonding method includes following operations. A wafer is provided with multiple semiconductor dies on an adhesive film held by a frame element. A semiconductor die is lifted up from the wafer by an ejector element. The semiconductor die is picked up with a collector element. The semiconductor die is flip-chipped with the collector element. An alignment check is performed to determine a position of the semiconductor die, so as to determine a process tolerance between a center of the collector element and a center of the semiconductor die. The semiconductor die with the collector element is transferred to a location underneath a bonder element based on the process tolerance of the alignment check. The semiconductor die is picked up from the collector element by the bonder element. The semiconductor die is bonded to a carrier by the bonder element.

Abstract: Some embodiments of the present disclosure relate to a semiconductor structure including a first conductive wire disposed over a substrate. A dielectric liner is arranged along sidewalls and an upper surface of the first conductive wire and is laterally surrounded by a first dielectric layer. The dielectric liner and the first dielectric layer are different materials. A conductive via is disposed within a second dielectric layer over the first conductive wire. The conductive via has a first lower surface disposed over the first dielectric layer and a second lower surface below the first lower surface and over the first conductive wire.

Abstract: The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.

Abstract: The present disclosure relates to a method and apparatus for cleaning a substrate. The method includes rotating a substrate disposed on a substrate support and spraying a front side of the substrate using steam through a front side nozzle assembly. A back side of the substrate is sprayed using steam through a back side dispenser assembly. A heated chemical is dispensed over the front side of the substrate.

Abstract: An MRAM device includes a bottom electrode over a substrate, a magnetic tunnel junction (MTJ) structure on the bottom electrode and a top electrode on the MTJ structure. The MRAM device also includes spacers on sidewalls of the top electrode and the MTJ structure. The MRAM device further includes a first etch stop layer on the spacers. A bottommost surface of the first etch stop layer covers a topmost surface of the spacers. In addition, the MRAM device includes a top electrode via on the top electrode and the first etch stop layer.

Abstract: A semiconductor structure includes a substrate, a gate structure, source/drain epitaxial structures, a contact structure, a first via structure, a metal line, a hard mask layer, a spacer layer, and a second via structure. The gate structure is formed over the substrate. The source/drain epitaxial structures are formed on opposite sides of the gate structure. The contact structure is formed over one of the source/drain epitaxial structures. The first via structure is formed over the contact structure. The metal line is electrically connected to the first via structure. The hard mask layer is formed over the metal line. The spacer layer is formed over a top surface of the hard mask layer and over a sidewall of metal line. The second via structure is formed over the metal line through the spacer layer.

Abstract: An energy storage and generation device has a motor, at least one renewable energy generator, a generator configured to be driven by the motor, a first storage unit, and a second storage unit. The first storage unit is for storing electrical energy generated by the generator, and the second storage unit is electrically connected between the at least one renewable energy generator and the motor.

Abstract: Nitrogen-doped CZ silicon crystal ingots and wafers sliced therefrom are disclosed that provide for post epitaxial thermally treated wafers having oxygen precipitate density and size that are substantially uniformly distributed radially and exhibit the lack of a significant edge effect. Methods for producing such CZ silicon crystal ingots are also provided by controlling the pull rate from molten silicon, the temperature gradient and the nitrogen concentration. Methods for simulating the radial bulk micro defect size distribution, radial bulk micro defect density distribution and oxygen precipitation density distribution of post epitaxial thermally treated wafers sliced from nitrogen-doped CZ silicon crystals are also provided.

Abstract: A method of chemical mechanical polishing includes bringing a substrate having a conductive layer disposed over a semiconductor wafer into contact with a polishing pad, generating relative motion between the substrate and the polishing pad, monitoring the substrate with an in-situ electromagnetic induction monitoring system as the conductive layer is polished to generate a sequence of signal values that depend on a thickness of the conductive layer, determining a sequence of thickness values for the conductive layer based on the sequence of signal values, and at least partially compensating for a contribution of conductivity of the semiconductor wafer to the signal values.

Abstract: An amplifier includes a first stage and a second stage. The first stage includes a floating current source to maintain current within a threshold. The first stage also includes a local common mode feedback configured to provide gain to an input signal. Moreover, the second stage includes a driver that provides a load current to a load coupled to the amplifier.

Abstract: A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

Abstract: A semiconductor package includes a first integrated circuit, a plurality of first through vias and a plurality of fin-shaped through vias. The first through vias surround the first integrated circuit. The fin-shaped through vias are physically connected to the first through vias respectively, wherein the first through vias are disposed between the first integrated circuit and the fin-shaped through vias.

Abstract: A microphone array is configured to select an optimal pickup pattern of a microphone array including at least two microphones each associated with a predefined microphone pickup pattern. The optimal pickup pattern is selected from a list of predefined pickup patterns including the predefined microphone pickup patterns and predefined mixed pickup patterns. A method of selecting an optimal pickup pattern includes receiving microphone audio signals from the microphones to establish a plurality of microphone audio signals and mixing them in accordance with the plurality of predefined mixed pickup patterns to establish a plurality of mixed audio signals. Individual level characteristics of respective individual microphone audio signals and of respective individual mixed audio signals are determined, and an optimal pickup pattern is selected from the list of predefined pickup patterns based on the individual level characteristics.

Abstract: A semiconductor package assembly includes a circuit board, a heat dissipating element and a semiconductor device. The circuit board includes a conductive pattern. The heat dissipating element is located on the circuit board, where the heat dissipating element is connected to the conductive pattern. The semiconductor device is located on the circuit board and next to the heat dissipating element, where the semiconductor device is thermally connected to the heat dissipating element through the conductive pattern.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer over a substrate, a metal layer over the first dielectric layer, a first conductive structure passing through the metal layer and the first dielectric layer, a second conductive structure passing through the metal layer and the first dielectric layer, and a third conductive structure coupling the first conductive structure to the second conductive structure, and overlying a first portion of the metal layer between the first conductive structure and the second conductive structure, wherein an interface exists between the metal layer and at least one of the first conductive structure or the second conductive structure.

Abstract: A multi-accumulator multiply-and-accumulate (MAC) unit can include a multiplier and a plurality of accumulators. The multiplier can be configured to multiply a given element of a corresponding column of a first matrix and a plurality of elements of a corresponding row of a second matrix to generate a plurality of corresponding partial product elements that can be accumulated by corresponding ones of the plurality of accumulators.