Abstract: A chip package structure is provided. The chip package structure includes a substrate. The chip package structure also includes a first chip structure and a second chip structure over the substrate. The chip package structure further includes an anti-warpage bar between the first chip structure and the second chip structure. In addition, the chip package structure includes an underfill layer between the first chip structure and the second chip structure and between the anti-warpage bar and the substrate. A topmost surface of the underfill layer is lower than a top surface of the anti-warpage bar.

Abstract: Certain embodiments provide an intraocular lens (IOL) including a lens body having an anterior lens element and a posterior lens element, and an optical fluid in a cavity formed between the anterior lens element and the posterior lens element. The anterior lens element and the posterior lens element each comprise a lens material having a first Abbe number, and the optical fluid has a second Abbe number that is less than the first Abbe number.

Abstract: The disclosed embodiments provide a system for processing data. During operation, the system applies a first set of hash functions to a first entity identifier (ID) for a first entity to generate a first set of hash values. Next, the system produces a first set of intermediate vectors from the first set of hash values and a first set of lookup tables by matching each hash value in the first set of hash values to an entry in a corresponding lookup table in the first set of lookup tables. The system then performs an element-wise aggregation of the first set of intermediate vectors to produce a first embedding. Finally, the system outputs the first embedding for use by a machine learning model.

Abstract: A package structure includes a redistribution circuit structure, a wiring substrate, a semiconductor device, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has dielectric layers. The wiring substrate is disposed on the redistribution circuit structure. The semiconductor device is disposed on the redistribution circuit structure opposite to the wiring substrate. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure is partially embedded in the redistribution circuit structure and is partially embedded in the insulating encapsulation. The reinforcement structure includes reinforcement pattern layers and reinforcement vias. The reinforcement pattern layers and the dielectric layers are stacked alternately. The reinforcement vias penetrate through the dielectric layers to connect the reinforcement pattern layers. The reinforcement structure is electrically floating.

Abstract: A semiconductor device includes a substrate, a gate, a second dielectric layer, and a field plate. The substrate has a first dielectric layer, and a thickness of the first dielectric layer in a first area is greater than a thickness of the first dielectric layer in a second area outside the first area. The gate is located on the substrate and in the first area, the gate includes a first gate structure and a second gate structure, and the second gate structure is formed on a side of the first dielectric layer that is away from the substrate and covers a part of the first dielectric layer. The second dielectric layer covers the gate and the first dielectric layer. The field plate is located on the second dielectric layer and is disposed in both the first area and the second area.

Abstract: A circuit board etching device for improving etching factor, comprising: a circuit board conveying device, which laterally conveys a circuit board; a circuit forming etching tank and a first etchant spraying unit, the first etchant spraying unit sprays a first etchant on the etching surface of the circuit board; and a circuit modification etching tank and a second etchant spraying unit, the second etchant spraying unit sprays a second etchant on the etching surface of the circuit board, and make the etching speed of the circuit modification etching tank slower than the etching speed of the circuit forming etching tank, whereby having the effect of improving the etching factor of the circuit board

Abstract: An inspection apparatus for inspecting a semiconductor workpiece includes a testing stage, a first seal member, a testing clamp, a second seal member, a semiconductor workpiece, and a transducer. The testing stage has a cavity. The first seal member is disposed in the cavity. The first seal member is attached to a sidewall of the cavity. The testing clamp is movably coupled to the testing stage. The second seal member is attached to the testing clamp. The semiconductor workpiece is held between the testing stage and the testing clamp by the first seal member and the second seal member. The transducer is movably disposed above the testing stage.

Abstract: The present invention relates to methods for treating dermatitis and the use of a ?-1 adrenoceptor antagonist in manufacturing a pharmaceutical composition for treating dermatitis. The methods comprise the step of administering the pharmaceutical composition comprising a therapeutically effective amount of ?-1 adrenoceptor antagonist to a subject in need thereof.

Abstract: This invention provides a process or fabrication method of forming broadband anti-reflective (AR) coating over the mid-IR fluoride fiber for high power laser applications in mid-IR wavelength range. The AR coating consists of multiple-pair Lithium fluoride (LiF) and Al2O3, and was deposited by electron beam physical vapor deposition with an iron assistant source at low temperature (<60° C.). A thin encapsulation layer of Al2O3 was applied over the AR coating by atomic layer deposition technology. The measurements show the coating has a reflectivity of <1-1.5% in the range of 1.5-5.5 ?m. The laser induced damage threshold (LIDT) test shows the damage threshold is greater than 8.9 MW/cm2 with no sign of any damage on the coating exposed to atmosphere. The durability and environmental tests of the AR coating with PVD coated encapsulation layer show good humidity resistance in open air and no degradation of film quality and optical performance are observed.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

Abstract: An interconnect structure includes dielectric layer, a first conductive feature, a second conductive feature, a third conductive feature, and a dielectric fill. The first conductive feature is disposed in the dielectric layer. The second conductive feature is disposed over the first conductive feature. The second conductive feature includes a first conductive layer disposed over the first conductive feature, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. The first conductive layer, the second conductive layer and the third conductive layer have substantially the same width. The third conductive feature is disposed over the dielectric layer. The dielectric fill is disposed over the dielectric layer between the second conductive feature and the third conductive feature.

Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.

Abstract: Nitrogen-doped CZ silicon crystal ingots and wafers sliced therefrom are disclosed that provide for post epitaxial thermally treated wafers having oxygen precipitate density and size that are substantially uniformly distributed radially and exhibit the lack of a significant edge effect. Methods for producing such CZ silicon crystal ingots are also provided by controlling the pull rate from molten silicon, the temperature gradient and the nitrogen concentration. Methods for simulating the radial bulk micro defect size distribution, radial bulk micro defect density distribution and oxygen precipitation density distribution of post epitaxial thermally treated wafers sliced from nitrogen-doped CZ silicon crystals are also provided.

Abstract: In the microsphere preparation for chemoembolization therapy and nuclear medicine imaging of tumor, and a preparation method thereof, the microsphere is formed by means of using a polyvinyl alcohol derivative as a framework material and polymerizing, crosslinking and curing same with an N-acryl amino acid monomer. The microsphere can label radionuclide iodine and can also absorb load chemotherapeutic drugs.

Abstract: Provided are a package and a method of manufacturing the same. The package includes a first die, a second die, a bridge structure, an encapsulant, and a redistribution layer (RDL) structure. The first die and the second die are disposed side by side. The bridge structure is disposed over the first die and the second die to electrically connect the first die and the second die. The encapsulant laterally encapsulates the first die, the second die, and the bridge structure. The RDL structure is disposed over a backside of the bridge structure and the encapsulant. The RDL structure includes an insulating structure and a conductive pattern, the conductive pattern is disposed over the insulating structure and extending through the insulating structure and a substrate of the bridge structure, so as to form at least one through via in the substrate of the bridge structure.

Abstract: This application provides a network handover method and an apparatus. Before a terminal device is handed over from a first network to a second network, the terminal device sets up a first tunnel to a first interworking device, where a communication identifier, of the terminal device, in the first tunnel is a first identifier the first identifier is an identifier used in the first network by the terminal device, and the first interworking device is an interface device in the first network and oriented toward a network other than the first network. After the terminal device is handed over from the first network to the second network, the terminal device sends an update request to the first interworking device, where the update request to update the communication identifier to a second identifier, and the second identifier is an identifier used in the second network by the terminal device.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

Abstract: A semiconductor structure including an integrated circuit die and conductive bumps is provided. The integrated circuit die includes bump pads. The conductive bumps are disposed on the bump pads. Each of the conductive bumps includes a first pillar portion disposed on one of the bump pads and a second pillar portion disposed on the first pillar portion. The second pillar portion is electrically connected to one of the bump pads through the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. A package structure including the above-mentioned semiconductor structure is also provided.

Abstract: A memory processing unit (MPU) can include a first memory, a second memory, a plurality of processing regions and control logic. The first memory can include a plurality of memory regions. The plurality of memory regions can be organized in a plurality of memory blocks. The plurality of memory regions can be configured to store integer, B-float, and/or Group B-float encode data. The plurality of processing regions can be interleaved between the plurality of processing regions of the first memory. The plurality of processing regions can be organized in a plurality of core groups include a plurality of compute cores. The compute groups in the processing regions can be coupled to a plurality of adjacent memory blocks in the adjacent memory regions. The second memory can be coupled to the plurality of processing regions.

Abstract: Patients diagnosed with a cancer harboring an IDH-1 mutation can be treated by the administration of a therapeutically effective amount of a pharmaceutical composition comprising Compound 1, a selective inhibitor of 2-HG production from mIDH-1 enzymes including the R132 mutations R132C, R132H, R132L, R132G, and R132S.