Abstract: A monolithic three dimensional integrated circuit is provided. The monolithic three dimensional integrated circuit includes a first cell layer having a first cell having a first active component of the monolithic three dimensional integrated circuit. A second layer having a second cell including a second active component. The second cell layer is formed vertically above the first cell layer. The first cell layer having the first active component and the second cell layer having the second active component are formed on a single die. The first cell has a smaller metal pitch than the second cell. A buried via electrically couples the first active component of the first cell of the first cell layer with the second active component of the second cell of the second cell layer.

Abstract: According to an aspect of an embodiment, operations for trend monitoring of code repositories and related information are provided. The operations include identifying a set of repositories from a collection of repositories hosted on one or more web-based repository hosting systems and collecting repository metadata for each repository. The operations further include generating a set of topic tags by using one or more natural language processing-based methods and collecting a set of statistics associated with each of the generated set of topic tags. The operations further include generating a set of presentation data based on one or more of the identified set of repositories, the collected repository metadata, the generated set of topic tags, and the collected set of statistics. The operations further include controlling a user device to display the generated set of presentation data onto an electronic User Interface of the user device.

Abstract: A white light interferometric fiber-optic gyroscope based on a rhombic optical path difference bias structure includes a laser, a rhombic optical path difference bias structure, a fiber coil and a photodetector. The white light interferometric fiber-optic gyroscope adopts an all-fiber structure to simplify the complexity of a gyroscope system and reduce the overall cost. A white light interferometric demodulation algorithm is used to realize linear output of rotation rate signals.

Abstract: A method of providing a parent container image may include obtaining container image names, obtaining layer hashes, constructing a structured database, and returning a parent container image. The container image names may be of container images that include static executable software for running a process. The layer hashes may be obtained for each of the container images. The structured database may be based on relationships between the container images, which may be identified using the layer hashes. The parent container image may be returned in response to a query regarding a container image. The parent container image may be identified using the structured database.

Abstract: According to an aspect of an embodiment, operations include deploying a trigger function on a computing system for detecting an electronic trigger event associated with a first Application Programming Interface (API) provider. The operations further include deploying a rule function for applying at least one trigger rule on event data and deploying an action function for generating at least one API call to a second API provider based on whether the event data satisfies the at least one trigger rule. The operations further include deploying a set of API gateways for enabling a workflow system to invoke at least one of: the deployed trigger function, the deployed rule function, and the deployed action function. The operations further include generating a workflow template of an API mashup based on information associated with the deployed functions and API gateways and posting the generated workflow template to the workflow system.

Abstract: A monolithic three-dimensional (3D) integrated circuit (IC) device includes a lower tier including a lower tier cell and an upper tier arranged over the lower tier. The upper tier has a first upper tier cell and a second upper tier cell separated by a predetermined lateral space. A monolithic inter-tier via (MIV) extends from the lower tier through the predetermined lateral space, and the MIV has a first end electrically connected to the lower tier cell and a second end electrically connected to the first upper tier cell.

Abstract: A high-voltage flip-chip semiconductor light-emitting device includes a substrate, at least two semiconductor light-emitting units, an isolation trench, a conducting layer, an isolating layer, a connecting layer, and a Bragg reflection layer. The semiconductor light-emitting units and the conducting layer are sequentially disposed on the substrate. The isolation trench is formed between the semiconductor light-emitting units. The isolating layer partially covers the conducting layer. The connecting layer is disposed on the isolating layer and electrically connects the semiconductor light-emitting units. The Bragg reflection layer covers the connecting layer and the isolating layer.

Abstract: A method of making an integrated circuit includes steps of etching an opening in an insulating mask to expose a first dummy contact on a backside of the integrated circuit, depositing a conductive material into the opening, the conductive material contacting a sidewall of the first dummy contact, and recessing the conductive material to expose an end of the first dummy contact. The method also includes steps of depositing an insulating material over the conductive material in the opening, removing the first dummy contact from the insulating mask to form a first contact opening, and forming a first conductive contact in the first contact opening, the first conductive contact being electrically connected to the conductive material.

Abstract: Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.

Abstract: A semiconductor device, including a first metal strip extending in a first direction on a first plane; a second metal strip extending in the first direction on a second plane over the first metal strip; a third metal strip immediate adjacent to the second metal strip and extending in the first direction on the second plane; and a fourth metal strip immediate adjacent to the third metal strip and extending in the first direction on the second plane; wherein the first metal strip and the second metal strip are directed to a first voltage source; wherein a distance between the second metal strip and the third metal strip is greater than a distance between the third metal strip and the fourth metal strip.

Abstract: A fabrication method of a semiconductor substrate includes: performing a chemical mechanical polishing process on a silicon carbide wafer; and performing a heating process on the silicon carbide wafer to remove a naturally formed oxide layer, to remove contaminants, to obtain a scratch-free surface, and to planarize, wherein the heating process includes: heating a chamber of a furnace and the silicon carbide wafer to T degrees Celsius for a time t, and introducing hydrogen, argon, nitrogen, or/and hydrogen chloride into the chamber; and then cooling down the furnace.

Abstract: Generating a circuit layout is provided. A circuit layout associated with a circuit is received. A parallel pattern recognition is performed on the circuit layout. Performing the parallel pattern recognition includes determining that there is a parallel pattern in the circuit layout. In response to determining that there is a parallel pattern in the circuit layout, a cell swap for a first cell associated with the parallel pattern with a second cell is performed. After the cell swap for the first cell, engineering change order routing is performed to connect the second cell in the circuit layout. An updated circuit layout having the second cell is provided.

Abstract: In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess.

Abstract: A method of forming a semiconductor device includes forming a wafer having an ion-implanted silicon layer, wherein the ion-implanted silicon layer is disposed between a first insulator layer and a second insulator layer inside the wafer; forming an active region over the ion-implanted silicon layer; forming an active device in the active region; and forming a conductive via to couple the ion-implanted silicon layer and the active device.

Abstract: Apparatus and methods for back side routing a data signal in a semiconductor device are described. In one example, a described semiconductor cell structure includes: a dummy device region at a front side of the semiconductor cell structure; a metal layer including a plurality of metal lines at a back side of the semiconductor cell structure; a dielectric layer formed between the dummy device region and the metal layer; an inner metal disposed within the dielectric layer; at least one first via that is formed through the dielectric layer and electrically connects the inner metal to the plurality of metal lines at the back side; and at least one second via that is formed in the dielectric layer and physically coupled between the inner metal and the dummy device region at the front side.

Abstract: A semiconductor structure including a first conductive layer, a second conductive layer situated above the first conductive layer, and a via extending diagonally between the second conductive layer and the first conductive layer to electrically connect the first conductive layer to the second conductive layer.

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.

Abstract: A method and system of solving a large-scale complex combinatorial problem including receiving the large-scale complex combinatorial problem as an input, converting a decision variable space of the large-scale complex combinatorial problem into a plurality of basic attribute units which correspond to a subset of total decision variables of the large-scale complex combinatorial problem, decomposing the large-scale complex combinatorial problem into a plurality of sub-problems of the plurality of basic attribute units, using a optimization solver, solving the plurality of sub-problems in parallel, outputting a plurality of candidate solutions corresponding to the solutions of the plurality of sub-problems, and using a optimization solver and the plurality of candidate solutions, solving the large scale complex combinatorial problem.

Abstract: According to an aspect of an embodiment, operations may include receiving a first input corresponding to a selection of a combinatorial optimization problem and receiving a set of datapoints as input. The operations may further include generating a first quadratic unconstrained binary optimization (QUBO) formulation based on an objective function for the combinatorial optimization problem and the received set of datapoints. The operations may further include selecting a first privacy setting and encoding the first QUBO formulation based on the selected privacy setting to generate a second QUBO formulation. The operations may further include submitting the generated second QUBO formulation to an optimization solver machine and receiving a first solution of the second QUBO formulation. The operations may further include decoding the first solution to produce a second solution and publishing an output of the combinatorial optimization problem on a user device based on the second solution.

Abstract: A method comprises receiving vehicle data comprising information associated with a plurality of sensors of autonomous vehicle and segmenting the received vehicle data into non-public data and public data. The method further comprises partitioning the public data into a plurality of data partitions and generating a plurality of data levels of the public data. Each data level of the plurality of data levels is generated according to an access level of a plurality of access levels and includes one or more data partitions of the plurality of data partitions in an encrypted form. The method further comprises transmitting the generated plurality of data levels to a group of electronic devices. Each electronic device of the group of electronic devices retrieves, according to one of the plurality of access levels, at least a portion of the public data from the transmitted plurality of data levels.