Abstract: A semiconductor light-emitting device includes a light-transmissible substrate, and a semiconductor light-emitting stack. The light-transmissible substrate is made of a first material, and has a first surface and a second surface opposite to the first surface. The first surface has a first region, and a second region which is formed with a plurality of protruding portions and a plurality of recessed portions formed therebetween. The recessed portions are disposed at a level lower than that of the first region relative to the second surface. The semiconductor light-emitting stack is disposed on the first region of the first surface along a stacking direction.

Abstract: A method for breeding a virtual pet is provided, including: displaying a mating market interface, the mating market interface including virtual pets in a mating state; selecting a paternal virtual pet from the virtual pets in the mating state via the mating market interface according to a first operation; displaying a pet breeding interface, the pet breeding interface including a paternal pet field and a maternal pet field, and the paternal virtual pet having a first pet image being displayed in the paternal pet field; adding a maternal virtual pet having a second pet image to the maternal pet field according to a second operation; and displaying a breeding result interface comprising a filial virtual pet when breeding succeeds, the filial virtual pet having a third pet image generated based on a genetic inheritance rule according to the first pet image and the second pet image.

Abstract: An ultraviolet light-emitting device includes a substrate including surface portions, a light-emitting structure including first and second semiconductor layers and an active layer, a first metallic contact electrode, and a second metallic contact electrode. The first and second metallic contact electrodes disposed on the light-emitting structure are respectively electrically connected to the first and second semiconductor layers. The first metallic contact electrode has at least one outer electrode section positioned between the active layer and a laser-cut surface portion. The active layer and the laser-cut surface portion are spaced apart by a minimum distance ranging from 30 ?m to 100 ?m.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first conductive pattern disposed within a first region from a top view perspective and extending along a first direction, a first phase shift circuit disposed within the first region, a first transmission circuit disposed within a second region from the top view perspective, and a first gate conductor extending from the first region to the second region along a second direction perpendicular to the first direction. The first phase shift circuit and the first transmission circuit are electrically connected with the first conductive pattern through the first gate conductor.

Abstract: Methods and devices are described herein for random cut patterning. A first metal line and a second metal line are formed within a cell of a substrate and extend in a vertical direction. A third metal line and a fourth metal line are formed within the cell and are perpendicular to the first metal line and the second metal line, respectively. A first circular region at one end of the first metal line is formed using a first patterning technique and a second circular region at one end of the second metal line is formed using a second patterning technique. The first circular region is laterally extended using a second patterning technique to form the third metal line and the second circular region is laterally extended using the second patterning technique to form the fourth metal line.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: Disclosed is a light-emitting diode which includes a light-emitting epitaxial layered unit, an insulation layer, a transparent conductive layer, a protective layer, a first electrode, and a second electrode. The light-emitting epitaxial layered unit includes a first semiconductor layer, a second semiconductor layer, and a light-emitting layer sandwiched between the first and second semiconductor layers, and has a first electrode region which includes a pad area and an extension area. The insulation layer is disposed on the first semiconductor layer and at the extension area of the first electrode region. Also disclosed is a method for manufacturing the light-emitting diode.

Abstract: Operations may include obtaining source code describing an optimization problem. The operations may include identifying problem parameters associated with the optimization problem such that a specialized computing system may be enabled to solve the optimization problem. The operations may include extracting one or more first parameters of the problem parameters from the source code. The operations may include identifying one or more second parameters of the problem parameters that are not included in the source code. A user may be prompted via a GUI for input relating to the one or more second parameters. The operations may include compiling the extracted first parameters and the user-provided second parameters as input parameters of the specialized computing system. The operations may include providing the input parameters to the specialized computing system such that the specialized computing system is able to solve the optimization problem.

Abstract: An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.

Abstract: A semiconductor device includes: a substrate; an ion-implanted silicon layer disposed in the substrate; a first insulator layer disposed over the ion-implanted silicon layer; an active device disposed over the first insulator layer; and a conductive via configured to penetrate the first insulator layer for coupling the ion-implanted silicon layer and the active device.

Abstract: An electronic device includes an integrated circuit and a smart film layer. Integrated circuit is configured to output a control signal. Smart film layer is coupled to integrated circuit and includes a first substrate, a second substrate, a liquid crystal layer, a transparent glue layer, a cover, and at least one touch electrode layer. Second substrate is located on first substrate. Liquid crystal layer is located between first substrate and second substrate. Transparent glue layer is located on second substrate. Cover is located on transparent glue layer. At least one touch electrode layer is located between two of first substrate, second substrate, liquid crystal layer, transparent glue layer, or cover. At least one touch electrode layer is configured to transmit a touch signal or at least one touch electrode layer is configured to control liquid crystal layer to present in transparent states according to control signal of integrated circuit.

Abstract: A method is disclosed that includes the operations below: determining, by a processing unit, that arrival times of a lot arrived at N process stages are less than processing times of the lot predetermined to be processed at the N process stages, N being a positive integer; comparing, by the processing unit, idle times of multiple tools in the N process stages; and processing the lot with a first tool of the tools at each one of the N process stages, wherein the first tool of the tools has a shortest idle time.

Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of first metal strips extending in a first direction on a first plane; and forming a plurality of second metal strips extending in the first direction on a second plane over the first plane by executing a photolithography operation with a single mask, wherein a first second metal strip (FIG. 1, 131) is disposed over a first first metal strip; wherein the first first metal strip and the first second metal strip are directed to a first voltage source; wherein a distance between the first second metal strip and a second second metal strip immediate adjacent to the first second metal strip is greater than a distance between the second second metal strip and a third second metal strip immediate adjacent to the second second metal strip.

Abstract: An integrated circuit (IC) device includes a first plurality of active areas extending in a first direction and having a first pitch in a second direction perpendicular to the first direction, and a second plurality of active areas extending in the first direction, offset from the first plurality of active areas in the first direction, and having a second pitch in the second direction. A ratio of the second pitch to the first pitch is 3:2.

Abstract: The disclosure relates to an expression method of a Haemocoagulase Acutus (Halase) recombinant protein. The method includes the following steps: (1) optimizing a halase gene; (2) performing Polymerase Chain Reaction (PCR) amplification on an optimized halase gene; (3) constructing an Agkis-pMCX expression vector, transforming plasmids to competent cells of an Escherichia coli for amplification, screening in an Amp-resistant manner for positive cloning, sequencing and extracting recombinant plasmids with correct sequencing; (4) transfecting recombinant plasmids to CHO cells; and (5) expressing the recombinant protein and identifying. According to the expression method, a recombinant halase is expressed first using the CHO cells cultured in a serum-free suspension manner; and by utilizing a bioengineering means, the actual production problems of insufficient raw material sources and unstable quality of a snake venom product are solved successfully.

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.

Abstract: A semiconductor device includes a semiconductor layered structure, an electrode unit, and an anti-adsorption layer. The electrode unit is disposed on an electrode connecting region of the semiconductor layered structure, and is a multi-layered structure. The anti-adsorption layer is disposed on a top surface of the electrode unit opposite to the semiconductor layered structure. Also disclosed herein is a light-emitting system including the semiconductor device.

Abstract: Disclosed is a new drug application of a Pithecellobium clypearia Benth Extract (EA), and particularly is a method of the EA used for treating multiple diseases caused by drug resistant bacteria infection. Related drug resistant bacteria include a Multi-Drug Resistant (MDR) Acinetobacter baumannii (MDRAB), an MDR Pseudomonas aeruginosa (MDRPA), an Extended-Spectrum Beta-Lactamase (ESBL) producing Escherichia coli (ECO) and an ESBL-producing Klebsiella pneumonia (KPN).

Abstract: An integrated circuit includes conductive rails that are disposed in a first conductive layer and separated from each other in a layout view, signal rails disposed in a second conductive layer different from the first conductive layer, at least one first via coupling a first signal rail of the signal rails to at least one of the conductive rails, and at least one first conductive segment. The first signal rail transmits a supply signal through the at least one first via and the at least one of the conductive rails to at least one element of the integrated circuit. The at least one first via and the at least one first conductive segment are disposed above first conductive layer. The at least one first conductive segment is coupled to the at least one of the conductive rails and is separate from the first signal rail.