Abstract: An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.

Abstract: Disclosed in the present invention are a heterocyclic compound, an application thereof and a pharmaceutical composition comprising the same. Provided by the present invention are a heterocyclic compound represented by formula I or a pharmaceutically acceptable salt thereof. The compound has a novel structure and a good inhibitory activity against autotaxin (ATX).

Abstract: A device including first nanosheet structures each including a first number of nanosheets, second nanosheet structures each including a second number of nanosheets that is different than the first number of nanosheets, and a plurality of rows including first rows and second rows. Where each of the first nanosheet structures is in a respective one of the first rows, each of the second nanosheet structures is in a respective one of the second rows, at least two of the first rows are adjacent one another, and at least two of the second rows are adjacent one another.

Abstract: According to an aspect of an embodiment, operations for detection of API compatibility across software versions are provided. The operations may include receiving an input associated with a software application. The operations may further include determining first information. The operations may further include extracting a set of data from one or more web-based sources based on the determined first information. The operations may further include executing a set of operations including one or more pattern searching operations on the extracted set of data to generate a compatibility result. The operations may further include controlling a display device based on the generated compatibility result. The display device may be controlled to display assistive information which informs about a compatibility of the one or more APIs or the functions used in the source code of the software application with respect to the second version of the software.

Abstract: The compound represented by formula (I), and racemates, stereoisomers, tautomers, isotopic markers, nitrogen oxides, solvates, polymorphs, metabolites, esters, pharmaceutically acceptable salts, or prodrugs thereof have ROCK inhibitory activity. The compound represented by formula (1) has good safety, good metabolic stability, and a low risk of potential hepatotoxicity. Further, the compound represented by formula (I) has a simple preparation method and is easy to purify, and therefore has good application prospects.

Abstract: A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

Abstract: An online concierge shopping system identifies recipes to users to encourage them to include items from the recipes in orders. The online concierge system generates a recipe vector for each recipe based on items included in a recipe. A dimension of a recipe vector identifies an item included in a corresponding recipe and may include an importance score of the item to the recipe. The importance score of an item to a recipe is based on a term frequency of the item in the recipe and an inverse document frequency of the item across multiple recipes. The online concierge system determines overlap between items in recipe vectors an order vector generated from items included in an order from a user and selects a recipe for the user based on overlapping items in the recipe vector and in the order vector.

Abstract: In some embodiments, an integrated circuit device includes a substrate having a frontside and a backside; one or more active semiconductor devices formed on the frontside of the substrate; conductive paths formed on the frontside of the substrate; and conductive paths formed on the backside of the substrate. At least some of the conductive paths formed on the backside of the substrate, and as least some of the conductive paths formed on the front side of the substrate, are signal paths among the active semiconductor devices. In in some embodiments, other conductive paths formed on the backside of the substrate are power grid lines for powering at least some of the active semiconductor devices.

Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

Abstract: A method of deploying an unmanned aerial vehicle (UAV) operation system may be provided. A method may include estimating an amount of traffic for one or more routes based on a demand of the one or more routes. The method may also include determining a required number of docking stations for each route of the one or more routes based on the estimated amount of traffic for the route, a distance of the route, and a maximum travel distance for a UAV. Further, the method may include installing the required number of docking stations for each route of the one or more routes, wherein each docking station of the required number of docking stations including at least one of a power supply, a wireless charger, a communication module, a control module, and a camera.

Abstract: A semiconductor device includes a cell. The cell includes an active area, gates, at least one gate via and at least one contact via. The active area includes forbidden regions. The gates are disposed across the active area. The at least one gate via is coupled with one of the gates. The at least one contact via is coupled with at least one conductive segment each corresponding to a source/drain of a transistor. In a layout view, one of the forbidden regions abuts a region of an abutted cell in which at least one of a gate via or a contact via of the abutted cell is disposed. In a layout view, the least one of the at least one gate via or the at least one contact via is arranged within the active area and outside of the forbidden regions. A method is also disclosed herein.

Abstract: A method of manufacturing a semiconductor device including: arranging a first and a second gate strip separating in a first distance, wherein each of the first and the second gate strip is a gate terminal of a transistor; depositing a first contact via on the first gate strip; forming a first conductive strip on the first contact via, wherein the first conductive strip and the first gate strip are crisscrossed from top view; arranging a second and a third conductive strip, above the first conductive strip, separating in a second distance, wherein each of the second and the third conductive strip is free from connecting to the first conductive strip, the first and the second conductive strip are crisscrossed from top view. The first distance is twice as the second distance. A length of the first conductive strip is smaller than two and a half times as the first distance.

Abstract: A light-emitting device includes a semiconductor light-emitting stack and a distributed Bragg reflector (DBR) structure. The semiconductor light-emitting stack includes a light-emitting layer. The DBR structure is disposed on the semiconductor light-emitting stack and includes a plurality of first dielectric material layers and a plurality of second dielectric material layers that are alternately stacked on the semiconductor light-emitting stack. The first dielectric material layer has a first refractive index, and the second dielectric material layer has a second refractive index. The first refractive index is lower than the second refractive index. The second dielectric material layer has an optical thickness that is smaller than that of the first dielectric material layer.

Abstract: A semiconductor device includes first, second, and third conductive regions and first and second active regions. The first conductive region has a first width and extends along a first direction. The second conductive region has a second width and extends along the first direction. The first width is greater than the second width. The first active region has a third width and extends along the first direction. The second active region has a fourth width and extends along the first direction. The third width is less than the fourth width. The third conductive region extends along a second direction and is electrically connected to the first conductive region. The second direction is different from the first direction. The first and second active regions are neighboring active regions.

Abstract: A light-emitting device includes a semiconductor light-emitting stack, first and second electrodes, an insulating layer, and a passivation layer. Each of the first and second electrodes is disposed on the semiconductor light-emitting stack. The insulating layer at least partially covers the semiconductor light-emitting stack. The passivation layer is disposed on the insulating layer, and covers the semiconductor light-emitting stack and a side surface of each of the first and second electrodes, to expose an upper surface of each of the first and second electrodes. The first electrode and the second electrode are separated by a distance that is greater than 0 ?m and that is not greater than 80 ?m.

Abstract: A semiconductor structure includes a plurality of cells. Each cell has a plurality of transistors, a plurality of inner metal lines, two first backside power lines and one second backside power line. The inner metal lines, the first backside power lines and the second backside power line are disposed on a back side of the transistors. The inner metal lines, the first backside power lines and the second backside power line extend along a first axis. The second backside power line is disposed between the two first backside power lines. The inner metal lines are electrically connected to the first backside power lines and the transistors, and electrically connected to the second backside power line and the transistors. The cells are arranged along a second axis, the second axis being vertical to the first axis.

Abstract: A semiconductor structure includes: a first gate structure and a second gate structure extending in a first direction; a first base level metal interconnect (M0) pattern extending in a second direction perpendicular to the first direction; a second M0 pattern extending in the second direction; a third M0 pattern located between the first and second gate structures and extending in the first direction, two ends of the third M0 pattern connected to the first M0 pattern and the second M0 pattern, respectively; a fourth M0 pattern and a fifth M0 pattern located between the first and second M0 patterns and extending in the second direction. A distance between the fourth M0 pattern and the first M0 pattern in the first direction is equal to a minimum M0 pattern pitch, and a distance between the fourth M0 pattern and the second M0 pattern is equal to the minimum M0 pattern pitch.

Abstract: A method may include providing access to a first application programming interface (API) provided by a first party and a second API provided by a second party. The method may also include collecting a first set of API data sources related to the first API and a second set of API data sources related to the second API. The method may additionally include using a deep learning model to predict a privacy trustworthiness level for the first API and the second API, and disabling access to the first API based on the privacy trustworthiness level of the first API being below a threshold level.

Abstract: A two-way signal positioning method and a two-way signal positioning system thereof are disclosed. The method includes the following steps: controlling a locating device to be measured to transmit a plurality of positioning signals of a plurality of transmission powers; causing a plurality of known locating devices to receive the plurality of positioning signals and return a plurality of response signals to the locating device to be measured; recording the strengths of the plurality of positioning signals, the strengths of the plurality of response signals, the plurality of corresponding receiving times and the coordinates of the plurality of known locating devices to a database; identifying the known locating devices corresponding to the stronger signals; and obtaining a signal strength-distance function and a signal strength-distance standard deviation function from the database so as to identify the device location of the locating device to be measured.

Abstract: A substrate processing apparatus includes a process station for processing a substrate; a cassette station integrated with the process station; a substrate carriage equipped for transferring the substrate between said process station and the cassette station through a passage located at an interface between the process station and said cassette station; and a substrate scanner equipped at said interface between the process station and the cassette station for capturing surface image data during transportation of the substrate that passes through the passage.