Abstract: A light-emitting device includes a substrate, a first type semiconductor layer, a protrusion, and a first reflection structure. The first type semiconductor layer is disposed on a surface of the substrate, and has a surface that has first and second conductive regions. The first type semiconductor layer is made of AlxGa1-xN, and x ranges from 0 to 1. A protrusion includes an active layer and a second type semiconductor layer that are sequentially disposed on the first conductive region of the surface of the first type semiconductor layer in such order. A first reflection structure is disposed in the protrusion, and penetrates through the second type semiconductor layer, the active layer of the protrusion and into the first type semiconductor layer. The light-emitting device emits light that has an emission wavelength ranging from 200 nm to 320 nm.

Abstract: A semiconductor light-emitting device includes a semiconductor light-emitting stack and an insulating light-transmissive layer. The semiconductor light-emitting stack includes an active layer and has a light-emitting surface. The insulating light-transmissive layer is disposed on the light-emitting surface and includes a base and a grade index structure. The base has a first refractive index. The grade index structure is disposed on the base in a way that the base is disposed between the semiconductor light-emitting stack and the graded index structure. The graded index structure includes at least two films and has a gradually varying refractive index which gradually decrease in a direction away from the base, and which is greater than the first refractive index. A light-emitting apparatus including the semiconductor light-emitting device and a sealing resin is also provided.

Abstract: An Ethernet power supply receives a DC voltage through a bus positive terminal and a bus negative terminal, and is coupled to a load device. The Ethernet power supply includes a first control module and a second control module. The first control module is used to provide a first control signal through the bus negative terminal to confirm whether the load device is a valid load. The second control module is used to connect or disconnect a coupling relationship between the bus positive terminal and the first control module according to the load device being connected or not.

Abstract: An Ethernet power supply receives a DC voltage through a bus positive terminal and a bus negative terminal, and is coupled to a load device. The Ethernet power supply includes a first control module and a second control module. The first control module provides a first control signal through the bus negative terminal to confirm whether the load device is a valid load. The second control module is used to connect or disconnect a coupling relationship between the bus positive terminal and the first control module according to whether the load device is connected to the Ethernet power supply.

Abstract: A semiconductor device includes a dielectric layer having a first surface and a second surface opposite to the first surface; an active region on the first surface of the dielectric layer; a power rail under the second surface of the dielectric layer, wherein the dielectric layer is between the active region and the power rail; a spacer physically dividing the active region into a first part and a second part, the first part and the second part being conductively isolated from each other by the spacer; an intermediate layer comprising: first and second conductive segments; and wherein the spacer joins the first conductive segment and the second conductive segment, and electrically isolates the first conductive segment from the second conductive segment, wherein a join length between the first conductive segment and the spacer is equal to a join length between the second conductive segment and the spacer.

Abstract: Generating a circuit layout is provided. A circuit layout associated with a circuit is received. A parallel pattern recognition is performed on the circuit layout. Performing the parallel pattern recognition includes determining that there is a parallel pattern in the circuit layout. In response to determining that there is a parallel pattern in the circuit layout, a cell swap for a first cell associated with the parallel pattern with a second cell is performed. After the cell swap for the first cell, engineering change order routing is performed to connect the second cell in the circuit layout. An updated circuit layout having the second cell is provided.

Abstract: Disclosed is a new drug application of a Pithecellobium clypearia Benth Extract (EA), and particularly is a method of the EA used for treating multiple diseases caused by drug resistant bacteria infection. Related drug resistant bacteria include a Multi-Drug Resistant (MDR) Acinetobacter baumannii (MDRAB), an MDR Pseudomonas aeruginosa (MDRPA), an Extended-Spectrum Beta-Lactamase (ESBL) producing Escherichia coli (ECO) and an ESBL-producing Klebsiella pneumonia (KPN).

Abstract: An electric vehicle charging system includes: an identification device configured to identify a vehicle and generate feature data associated with the vehicle, a computing device electrically coupled to the identification device, with the computing device configured to obtain a charging specification of the vehicle from a database according to the feature data, wherein the computing device generates a power-supply command associated with the charging specification, and a charging device electrically coupled to the computing device and comprising a plurality of connectors respectively having a power inserter, with the connectors configured to be electrically coupled to a plurality of vehicles with different charging specifications through the power inserters, wherein the charging device selects one of the connectors according to the power-supply command, and provides power to the selected connector.

Abstract: A semiconductor device includes a first cell. The first cell is surrounded by a castle-shaped forbidden region. The first cell includes a first active region, a second active region, and at least one via. The first active region and the second active region extend along a first direction and are separated from each other along a second direction traverse to the first direction. The first active region partially overlaps an upper region of the castle-shaped forbidden region, and the second active region partially overlaps a lower region of the castle-shaped forbidden region. The at least one via is arranged outside the castle-shaped forbidden region.

Abstract: A method may include obtaining training code and extracting features from the training code. The extracted features of the training code may be mapped to natural language code vectors by a deep neural network. A natural language search query requesting source-code suggestions may be received, and the natural language search query may be mapped to a natural language search vector by the deep neural network. The method may include mapping the natural language search query to the natural language search vector in the same or a similar method as mapping the extracted features of the training code to natural language code vectors, and the natural language search vector may be compared to the natural language code vectors. Source code responsive to the natural language search query may be suggested based on the comparison between the natural language search vector and the natural language code vectors.

Abstract: The present disclosure discloses a quantitative evaluation system and evaluation method for hemangioma. The evaluation system includes an image acquisition module, an image analysis module, a result evaluation module and a display module. The image acquisition module includes a light source device, an imaging device and a storage device. The image analysis module includes a digital signal processor and digital analysis software. The digital signal processor divides pixel points of the hemangioma image into a tumor image and a tumor side image. The digital analysis software calculates comprehensive red, green, blue (RGB) values of the tumor image and the tumor side image. The result evaluation module includes a therapeutic evaluation coefficient, and the therapeutic evaluation coefficient = tumor comprehensive RGB value - tumor-side comprehensive RGB value.

Abstract: In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess. In some embodiments, the method further includes partially exposing the semiconductor region in a second recess in the first dielectric material and selectively depositing the second dielectric material on the first dielectric material, but not the semiconductor region, in the second recess.

Abstract: A light-emitting diode includes a semiconductor light-emitting stack, a transparent conductive layer, a first current blocking layer, and a first electrode pad. The transparent conductive layer is disposed on the semiconductor light-emitting stack, and is formed with a first opening defined by an inner edge thereof. The first current blocking layer is formed on the semiconductor light-emitting stack, and is surrounded by and spaced apart from the inner edge of the transparent conductive layer by a first gap. The first electrode pad fully covers the first current blocking layer so as to permit the first electrode pad to be in contact with the semiconductor light-emitting stack through the first gap.

Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.

Abstract: An LED device includes an epitaxial layered structure, a current spreading layer, a first insulating layer and a reflective structure. The current spreading layer is formed on a surface of the epitaxial layered structure. The first insulating layer is formed over the current spreading layer, and is formed with at least one first through hole to expose the current spreading layer. The reflective structure is formed on the first insulating layer, extends into the first through hole, and contacts with the current spreading layer. The current spreading layer is formed with at least one opening structure to expose the surface of the epitaxial layered structure.

Abstract: An integrated circuit includes a strip structure having a front side and a back side. A gate structure is on the front side of the strip structure. The integrated circuit includes a plurality of channel layers above the front side of the strip structure, wherein each of the plurality of channel layers is enclosed within the gate structure. An isolation structure surrounds the strip structure. The integrated circuit includes a backside via in the isolation structure. An epitaxy structure is on the front side of the strip structure. The integrated circuit includes a contact over the epitaxy structure. The contact has a first portion on a first side of the epitaxy structure. The first portion of the contact extends into the isolation structure and contacts the backside via. The integrated circuit includes a backside power rail on the back side of the strip structure and contacting the backside via.

Abstract: Disclosed is a fused ring compound and an application thereof. Disclosed is a fused ring compound represented by formula I, a pharmaceutically acceptable salt, a stereoisomer, a tautomer, an isotope compound, a crystal form, a nitrogen oxide, a solvate, or a solvate of the pharmaceutically acceptable salt thereof. The fused ring compound of the present invention has high P2X4 antagonistic activity, excellent selectivity, low toxicity and excellent metabolic stability.

Abstract: A server includes a rack, a chassis, and a fan module. The chassis includes a supporting tray, a bracket, and a first electrical connector. The supporting tray is detachably disposed into the rack along an assembling direction substantially perpendicular to a normal direction thereof. The bracket is disposed at an end of the supporting tray. The first electrical connector is disposed on the bracket. The first electrical connector at least has one end movable or detachable with respect to the bracket along a direction substantially perpendicular to the assembling direction. The fan module is detachably disposed in the bracket along the assembling direction. The fan module includes a fan rack, a fan unit, and a second electrical connector. The fan unit is disposed in the fan rack. The second electrical connector is disposed on the fan rack. The second electrical connector is electrically connected to the first electrical connector.

Abstract: A heterocyclic compound, and a pharmaceutical composition thereof, a preparation method therefor, an intermediate thereof and an application thereof. The structure of the heterocyclic compound is as shown in formula (I) below. The compound has CDK7 inhibitory activity, and can be used to treat tumors and other diseases.

Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of gate strips, each gate strip is a gate terminal of a transistor; forming a plurality of first contact vias connected to a part of the gate strips; forming a plurality of first metal strips above the plurality of gate strips; connecting one of the first metal strips to one of the first contact vias; forming a plurality of second metal strips above the plurality of first metal strips, wherein the plurality of second metal strips are co-planar, each second metal strip and one of the first metal strips are crisscrossed from top view; a length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half times as the length between two adjacent gate strips.