Patents by Inventor Wei-Ting Chen

Wei-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device with shield for electromagnetic interference
    Patent number: 10510682
    Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Wei-Ting Chen, Chieh-Yen Chen
  • Package structure, semiconductor chip and method of fabricating the same
    Patent number: 10504835
    Abstract: A semiconductor chip including a die substrate, a plurality of first bonding structures, a plurality of conductive elements, at least one integrated device, a plurality of conductive posts and a protection layer is provided. The first bonding structures are disposed on the die substrate. The conductive elements are disposed on the die substrate adjacent to the first bonding structures. The integrated device is disposed on the die substrate over the first bonding structures, wherein the integrated device includes a plurality of second bonding structures and a plurality of conductive pillars, and the second bonding structures are hybrid bonded to the first bonding structures. The conductive posts are disposed on the conductive elements and surrounding the integrated device. The protection layer is encapsulating the integrated device and the conductive posts.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Wei-Ting Chen
  • Semiconductor structure
    Patent number: 10475755
    Abstract: A method of manufacturing a semiconductor structure includes providing a transceiver, forming a molding to surround the transceiver, forming a plurality of recesses extending through the molding, disposing a conductive material into the plurality of recesses to form a plurality of vias, disposing and patterning an insulating layer over the molding, the plurality of vias and the transceiver, and forming a redistribution layer (RDL) over the insulating layer, wherein the RDL comprises an antenna disposed over the insulating layer and a dielectric layer covering the antenna, and a portion of the antenna is extended through the insulating layer and is electrically connected with the transceiver.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Vincent Chen, Hung-Yi Kuo, Chuei-Tang Wang, Hao-Yi Tsai, Chen-Hua Yu, Wei-Ting Chen, Ming Hung Tseng, Yen-Liang Lin
  • Structure and Formation Method of Semiconductor Device Structure
    Publication number: 20190305115
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack.
    Type: Application
    Filed: June 17, 2019
    Publication date: October 3, 2019
    Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Wei-Ting Chen, Yu-Cheng Liu
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20190287914
    Abstract: A semiconductor structure includes an etching stop layer over an inter-layer dielectric (ILD) layer; a low-k dielectric layer over the etching stop layer; and a tapered conductor extending through the low-k dielectric layer and the etching stop layer and partially through the ILD layer; wherein the tapered conductor includes a recess disposed within the ILD layer and indented towards the etching stop layer and the low-k dielectric layer, and a protrusion surrounding the recess and protruded from the etching stop layer towards the ILD layer.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 19, 2019
    Inventors: WEI TING CHEN, CHE-CHENG CHANG, CHEN-HSIANG LU, YU-CHENG LIU
  • Achromatic metalens and metalens with reverse chromatic dispersion
    Patent number: 10408416
    Abstract: An optical device includes a substrate, a reflective layer disposed over the substrate, and a metalens disposed over the reflective layer. The metalens includes a plurality of nanopillars, the plurality of nanopillars together specifying a phase profile such that the metalens has a focal length that is substantially constant over a wavelength range of an incident light of about 490 nm to about 550 nm.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: September 10, 2019
    Assignee: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Mohammadreza Khorasaninejad, Zhujun Shi, Alexander Y. Zhu, Wei Ting Chen, Vyshakh Sanjeev, Federico Capasso
  • ELECTRONIC DEVICE
    Publication number: 20190250673
    Abstract: An electronic device includes a first body, a second body, a base, a first shaft structure, a second shaft structure, and a locking component. The second body is connected to the first body through the base. The first shaft structure includes a first shaft and a second shaft. The second body is pivoted to a first base portion of the base through the first shaft and a second base portion of the base through the second shaft. The second shaft structure includes a connecting component fixed to the first body and a third shaft pivoted to the first base portion and the connecting component. The first and second shafts are perpendicular to the third shaft. The locking component is slidably disposed between the second base portion and the first body and configured to lock or release a connection between the second base portion and the first body.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 15, 2019
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Ting Chen, Tzu-Chien Lai, Yen-Hsiao Yeh, Nien-Chen Lee, Yi-Chun Lin
  • HIGH PERFORMANCE VISIBLE WAVELENGTH META-AXICONS FOR GENERATING BESSEL BEAMS
    Publication number: 20190235139
    Abstract: An optical device comprises a substrate and a metasurface. The metasurface comprises a plurality of nanoscale elements disposed on the transparent substrate at different orientations. The orientations of the nanoscale elements define a phase profile such that the nanoscale elements convert an incident light into an output light propagating substantially without diffraction.
    Type: Application
    Filed: October 13, 2017
    Publication date: August 1, 2019
    Applicant: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Wei-Ting CHEN, Mohammadreza KHORASANINEJAD, Alexander Yutong ZHU, Jaewon OH, Robert Charles DEVLIN, Muhammad Aun Abbas ZAIDI, Federico CAPASSO
  • Structure and formation method of semiconductor device structure
    Patent number: 10326005
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Wei-Ting Chen, Yu-Cheng Liu
  • SUPER-DISPERSIVE OFF-AXIS META-LENSES FOR HIGH RESOLUTION COMPACT SPECTROSCOPY
    Publication number: 20190162592
    Abstract: A meta-lens having a phase profile includes a substrate and a plurality of nanostructures disposed on the substrate. The nanostructures together define the phase profile of the meta-lens. The phase profile achieves an off-axis focus. Each nanostructure is designed according to at least one design parameter of the nanostructure that imparts a phase shift of light passing through the nanostructure.
    Type: Application
    Filed: April 7, 2017
    Publication date: May 30, 2019
    Applicant: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Mohammadreza KHORASANINEJAD, Federico CAPASSO, Wei Ting CHEN, Jaewon OH
  • Semiconductor structure having tapered damascene aperture and method of the same
    Patent number: 10304774
    Abstract: A semiconductor structure having tapered damascene aperture is disclosed. The semiconductor structure including an etching stop layer over an inter-layer dielectric (ILD) layer, a low-k dielectric layer over the etching stop layer, and a tapered aperture at least going into the low-k dielectric layer; wherein the tapered aperture is filled with copper (Cu), a width of a mouth surface portion of the aperture tapers inwardly from a first, wider width to a second, narrower width at a bottom surface portion of the aperture, and the width of the bottom surface portion of the tapered aperture is less than 50 nm. Associated methods of fabricating a semiconductor structure are also disclosed.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei Ting Chen, Che-Cheng Chang, Chen-Hsiang Lu, Yu-Cheng Liu
  • META-LENSES FOR SUB-WAVELENGTH RESOLUTION IMAGING
    Publication number: 20190154877
    Abstract: A meta-lens having a phase profile includes a substrate and a plurality of nanostructures disposed on the substrate. Each individual nanostructure of the nanostructures imparts a light phase shift that varies depending on a location of the individual nanostructure on the substrate. The light phase shifts of the nanostructures define the phase profile of the meta-lens. The varying light phase shifts can be realized by, e.g., changing orientations of nanofins or changing diameters of nanopillars.
    Type: Application
    Filed: April 5, 2017
    Publication date: May 23, 2019
    Applicant: President and Fellows of Harvard College
    Inventors: Federico CAPASSO, Wei Ting CHEN, Robert Charles DEVLIN, Mohammadreza KHORASANINEJAD, Jaewon OH, Alexander ZHU, Charles ROQUES-CARMES, Ishan MISHRA
  • 3D MODELING METHOD BASED ON POINT CLOUD DATA
    Publication number: 20190122377
    Abstract: A 3D modeling method based on point cloud data for generating 3D object data corresponding to target object (50, 51) includes activating a 3D scanner (2) to obtain 2D images of the target object (50, 51) from different angles and a plurality of depths of the target object (50, 51); generating a plurality of point cloud data (60-64) based on the 2D images and the depths; performing a pre-modeling process on the plural point cloud data (60-64) to filter the plural point data (70-79) not belonging to the target object (50, 51) out of each point cloud data (60-64); and performing a 3D modeling process on the filtered point cloud data (60-64) to generate the 3D object data. The 3D object data generated by the present disclosed example via execution of the pre-modeling process has minimum noise and is appropriate for 3D print.
    Type: Application
    Filed: January 11, 2018
    Publication date: April 25, 2019
    Inventor: Wei-Ting CHEN
  • SEMICONDUCTOR MANUFACTURING METHOD
    Publication number: 20190122933
    Abstract: A method for manufacturing a semiconductor device includes forming first and second fins over a substrate, forming first and second dummy gate structures over the first and second fins, respectively, replacing the first and second dummy gate structures with first and second gate structures, respectively, and after replacing the first and second dummy gate structures, forming an insulating structure between the first and second gate structures.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng CHANG, Chih-Han LIN, Wei-Ting CHEN
  • Semiconductor Device With shield for Electromagnetic interference
    Publication number: 20190109096
    Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 11, 2019
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Wei-Ting Chen, Chieh-Yen Chen
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20190067222
    Abstract: A method of manufacturing a semiconductor structure includes providing a transceiver, forming a molding to surround the transceiver, forming a plurality of recesses extending through the molding, disposing a conductive material into the plurality of recesses to form a plurality of vias, disposing and patterning an insulating layer over the molding, the plurality of vias and the transceiver, and forming a redistribution layer (RDL) over the insulating layer, wherein the RDL comprises an antenna disposed over the insulating layer and a dielectric layer covering the antenna, and a portion of the antenna is extended through the insulating layer and is electrically connected with the transceiver.
    Type: Application
    Filed: October 29, 2018
    Publication date: February 28, 2019
    Inventors: VINCENT CHEN, HUNG-YI KUO, CHUEI-TANG WANG, HAO-YI TSAI, CHEN-HUA YU, WEI-TING CHEN, MING HUNG TSENG, YEN-LIANG LIN
  • PLANE CORRECTING DEVICE AND SEMICONDUCTOR TESTING APPARATUS INCLUDING THE SAME
    Publication number: 20190056430
    Abstract: A plane correcting device comprises a first base disposed on a test head of a semiconductor testing apparatus; a second base disposed on the prober stage of the semiconductor testing apparatus and opposite to the first base; a plurality of correcting rods disposed between the first base and the second base, wherein a protruding height of each correcting rods may be adjusted to correct the prober stage to a predetermined plane; and a plurality of fixing units disposed on the first base or the second base to fix relative position of the prober stage and the test head. The present invention also provides a semiconductor testing apparatus including the plane correcting device.
    Type: Application
    Filed: March 8, 2018
    Publication date: February 21, 2019
    Inventors: Po-Ju KU, Wei-Ting CHEN
  • PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME
    Publication number: 20190035877
    Abstract: A package structure has a chip, a molding compound encapsulating the chip and an inductor structure disposed above the chip. A vertical projection of the inductor structure at least partially overlaps with a vertical projection of the chip.
    Type: Application
    Filed: September 21, 2017
    Publication date: January 31, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chuei-Tang Wang, Tzu-Chun Tang, Wei-Ting Chen, Chieh-Yen Chen
  • SEMICONDUCTOR DEVICE WITH SHIELD FOR ELECTROMAGNETIC INTERFERENCE
    Publication number: 20190006288
    Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.
    Type: Application
    Filed: November 1, 2017
    Publication date: January 3, 2019
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Wei-Ting Chen, Chieh-Yen Chen
  • InFO Coil on Metal Plate with Slot
    Publication number: 20190006085
    Abstract: A structure includes an encapsulating material, and a coil including a through-conductor. The through-conductor is in the encapsulating material, with a top surface of the through-conductor coplanar with a top surface of the encapsulating material, and a bottom surface of the through-conductor coplanar with a bottom surface of the encapsulating material. A metal plate is underlying the encapsulating material. A slot is in the metal plate and filled with a dielectric material. The slot has a portion overlapped by the coil.
    Type: Application
    Filed: September 10, 2018
    Publication date: January 3, 2019
    Inventors: Chuei-Tang Wang, Wei-Ting Chen, Chieh-Yen Chen, Hao-Yi Tsai, Ming Hung Tseng, Hung-Yi Kuo, Chen-Hua Yu