Patents by Inventor Wei-Ting Chen

Wei-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structure
    Patent number: 10763229
    Abstract: A semiconductor structure includes a transceiver, a molding surrounding the transceiver, a plurality of vias extending through the molding, and a RDL disposed over the transceiver and the plurality of vias. In some embodiments, the RDL includes an antenna disposed over and electrically connected to the transceiver, and a dielectric layer surrounding the antenna. In some embodiments, the antenna includes an elongated portion extending over the molding and a via portion electrically connected to the transceiver.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Vincent Chen, Hung-Yi Kuo, Chuei-Tang Wang, Hao-Yi Tsai, Chen-Hua Yu, Wei-Ting Chen, Ming Hung Tseng, Yen-Liang Lin
  • Structure of semiconductor device structure having fins
    Patent number: 10686059
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Yu-Cheng Liu, Wei-Ting Chen
  • Structure and formation method of semiconductor device structure
    Patent number: 10686060
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Wei-Ting Chen, Yu-Cheng Liu
  • Electronic device
    Patent number: 10678307
    Abstract: An electronic device includes a first body, a second body, a base, a first shaft structure, a second shaft structure, and a locking component. The second body is connected to the first body through the base. The first shaft structure includes a first shaft and a second shaft. The second body is pivoted to a first base portion of the base through the first shaft and a second base portion of the base through the second shaft. The second shaft structure includes a connecting component fixed to the first body and a third shaft pivoted to the first base portion and the connecting component. The first and second shafts are perpendicular to the third shaft. The locking component is slidably disposed between the second base portion and the first body and configured to lock or release a connection between the second base portion and the first body.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: June 9, 2020
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Ting Chen, Tzu-Chien Lai, Yen-Hsiao Yeh, Nien-Chen Lee, Yi-Chun Lin
  • Super-dispersive off-axis meta-lenses for high resolution compact spectroscopy
    Patent number: 10634557
    Abstract: A meta-lens having a phase profile includes a substrate and a plurality of nanostructures disposed on the substrate. The nanostructures together define the phase profile of the meta-lens. The phase profile achieves an off-axis focus. Each nanostructure is designed according to at least one design parameter of the nanostructure that imparts a phase shift of light passing through the nanostructure.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: April 28, 2020
    Assignee: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Mohammadreza Khorasaninejad, Federico Capasso, Wei Ting Chen, Jaewon Oh
  • Semiconductor manufacturing method
    Patent number: 10629491
    Abstract: A method for manufacturing a semiconductor device includes forming first and second fins over a substrate, forming first and second dummy gate structures over the first and second fins, respectively, replacing the first and second dummy gate structures with first and second gate structures, respectively, and after replacing the first and second dummy gate structures, forming an insulating structure between the first and second gate structures.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Wei-Ting Chen
  • Semiconductor Device With Shield for Electromagnetic Interference
    Publication number: 20200118938
    Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Wei-Ting Chen, Chieh-Yen Chen
  • Packaged Semiconductor Devices and Packaging Methods
    Publication number: 20200118971
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a first molding material disposed around the integrated circuit die, and a through-via disposed within the first molding material. A first side of a redistribution layer (RDL) is coupled to the integrated circuit die, the through-via, and the first molding material. A second molding material is over a second side of the RDL, the second side of the RDL being opposite the first side of the RDL. The packaged semiconductor device includes an antenna over the second molding material.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Tzu-Chun Tang, Chuei-Tang Wang, Chun-Lin Lu, Wei-Ting Chen, Vincent Chen, Shou-Zen Chang, Kai-Chiang Wu
  • 3D modeling method based on point cloud data
    Patent number: 10621740
    Abstract: A 3D modeling method based on point cloud data for generating 3D object data corresponding to target object (50, 51) includes activating a 3D scanner (2) to obtain 2D images of the target object (50, 51) from different angles and a plurality of depths of the target object (50, 51); generating a plurality of point cloud data (60-64) based on the 2D images and the depths; performing a pre-modeling process on the plural point cloud data (60-64) to filter the plural point data (70-79) not belonging to the target object (50, 51) out of each point cloud data (60-64); and performing a 3D modeling process on the filtered point cloud data (60-64) to generate the 3D object data. The 3D object data generated by the present disclosed example via execution of the pre-modeling process has minimum noise and is appropriate for 3D print.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 14, 2020
    Assignees: XYZPRINTING, INC., KINPO ELECTRONICS, INC.
    Inventor: Wei-Ting Chen
  • IMMERSION META-LENS AT VISIBLE WAVELENGTHS FOR DIFFRACTION-LIMITED IMAGING
    Publication number: 20200103640
    Abstract: An optical imaging apparatus is disclosed. The optical imaging apparatus includes a metasurface lens including a substrate and a plurality of nano-structures patterned on a first side of the substrate. The optical imaging apparatus further includes imaging optics disposed in a spaced apart relationship with a second side of the substrate. The second side is opposite the first side on which the nano-structures are patterned. A surface of the imaging optics and the second side of the substrate define a space for accommodating an immersion fluid. The metasurface lens is configured to direct light incident on the plurality of nano-structures towards the imaging optics through the space accommodating the immersion fluid.
    Type: Application
    Filed: March 29, 2018
    Publication date: April 2, 2020
    Applicant: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Wei Ting CHEN, Alexander Yutong ZHU, Mohammadreza KHORASANINEJAD, Zhujun SHI, Federico CAPASSO, Vyshakh SANJEEV
  • HEAT CONDUCTIVE SPACER FOR PLASMA PROCESSING CHAMBER
    Publication number: 20200098549
    Abstract: A plasma processing chamber includes a chamber body and a lid assembly coupled to the chamber body to define a processing volume. The lid assembly includes a backing plate coupled to the chamber body, a diffuser with a plurality of openings formed therethrough, and a heat conductive spacer disposed between and coupled to the backing plate and the diffuser to transfer heat from the diffuser to the backing plate. The plasma processing chamber further includes a substrate support disposed within the processing volume.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Beom Soo PARK, Robin L. TINER, Jianheng LI, Sang Jeong OH, Lai ZHAO, Gaku FURUTA, Soo Young CHOI, Jeevan Prakash SEQUEIRA, Wei-Ting CHEN, Hsiao-Ling YANG, Cheng-Hang HSU, Won Ho SUNG, Hyun Young HONG
  • SEMICONDUCTOR STRUCTURE, PACKAGE STRUCTURE, AND MANUFACTURING METHOD THEREOF
    Publication number: 20200091063
    Abstract: A semiconductor structure including at least one integrated circuit component is provided. The at least one integrated circuit component includes a first semiconductor substrate and a second semiconductor substrate electrically coupled to the first semiconductor substrate, wherein the first semiconductor substrate and the second semiconductor substrate are bonded through a first hybrid bonding interface, and at least one of the first semiconductor substrate or the second semiconductor substrate includes at least one first embedded capacitor.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ting Chen, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20200075516
    Abstract: A semiconductor structure includes a transceiver, a molding surrounding the transceiver, a plurality of vias extending through the molding, and a RDL disposed over the transceiver and the plurality of vias. In some embodiments, the RDL includes an antenna disposed over and electrically connected to the transceiver, and a dielectric layer surrounding the antenna. In some embodiments, the antenna includes an elongated portion extending over the molding and a via portion electrically connected to the transceiver.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Inventors: VINCENT CHEN, HUNG-YI KUO, CHUEI-TANG WANG, HAO-YI TSAI, CHEN-HUA YU, WEI-TING CHEN, MING HUNG TSENG, YEN-LIANG LIN
  • SEMICONDUCTOR CHIP, PACKAGE STRUCTURE, AND PACAKGE-ON-PACKAGE STRUCTURE
    Publication number: 20200066631
    Abstract: A semiconductor chip including a die substrate, a plurality of first bonding structures, a plurality of conductive elements, at least one integrated device, a plurality of conductive posts and a protection layer is provided. The first bonding structures are disposed on the die substrate. The conductive elements are disposed on the die substrate adjacent to the first bonding structures. The integrated device is disposed on the die substrate over the first bonding structures, wherein the integrated device includes a plurality of second bonding structures and a plurality of conductive pillars, and the second bonding structures are hybrid bonded to the first bonding structures. The conductive posts are disposed on the conductive elements and surrounding the integrated device. The protection layer is encapsulating the integrated device and the conductive posts.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Wei-Ting Chen
  • SEMICONDUCTOR DEVICE, INTEGRATED FAN-OUT PACKAGE AND METHOD OF FORMING THE SAME
    Publication number: 20200020627
    Abstract: A semiconductor device, an integrated fan-out package and a method of forming the same are disclosed. In some embodiments, a semiconductor device includes a substrate, a conductive layer, a passivation layer and a bump structure. The substrate has at least one electronic component therein. The conductive layer has a plurality of lines patterns over and electrically connected to the at least one electronic component. The passivation layer is over the conductive layer. The bump structure has a plurality of protruding parts penetrating through the passivation layer and electrically connected to the lines patterns of the conductive layer.
    Type: Application
    Filed: July 16, 2018
    Publication date: January 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Wei-Ting Chen
  • Packaged semiconductor devices and packaging methods
    Patent number: 10510714
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a first molding material disposed around the integrated circuit die, and a through-via disposed within the first molding material. A first side of a redistribution layer (RDL) is coupled to the integrated circuit die, the through-via, and the first molding material. A second molding material is over a second side of the RDL, the second side of the RDL being opposite the first side of the RDL. The packaged semiconductor device includes an antenna over the second molding material.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Chun Tang, Chuei-Tang Wang, Chun-Lin Lu, Wei-Ting Chen, Vincent Chen, Shou-Zen Chang, Kai-Chiang Wu
  • Semiconductor package devices integrated with inductor
    Patent number: 10510660
    Abstract: The present disclosure provides an inductor structure. The inductor structure, comprising a first surface, a second surface intersecting with the first surface, a first conductive pattern and a second conductive pattern. The first conductive pattern is formed on the first surface. The second conductive pattern is formed on the second surface. The first conductive pattern is connected with the second conductive pattern.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Ting Chen, In-Tsang Lin, Vincent Chen, Chuei-Tang Wang, Chen-Hua Yu
  • Semiconductor device with shield for electromagnetic interference
    Patent number: 10510679
    Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Wei-Ting Chen, Chieh-Yen Chen
  • Electronic device with lateral-openable display
    Patent number: D895610
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: September 8, 2020
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Ting Chen, Tzu-Chien Lai, Yen-Hsiao Yeh, Nien-Chen Lee
  • Electronic device with flippable display
    Patent number: D895611
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: September 8, 2020
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Ting Chen, Tzu-Chien Lai, Yen-Hsiao Yeh, Nien-Chen Lee