Patents by Inventor Wei Wang

Wei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250086436
    Abstract: A channel encoding/decoding method and an apparatus, where the method includes: obtaining a plurality of pieces of first information based on a to-be-sent bit sequence, where each piece of first information includes a multi-dimensional time step feature, the multi-dimensional time step feature is determined based on a plurality of bits in the bit sequence, a plurality of bits corresponding to a multi-dimensional time step feature included in an ith piece of first information and a plurality of bits corresponding to a multi-dimensional time step feature included in an (i+1)th piece of first information are partially the same, and i is a positive integer; encoding the plurality of pieces of first information into second information; and sending the second information.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: Shengchen Dai, Wei Teng, Jian Wang, Rong Li, Jun Wang
  • Publication number: 20250085590
    Abstract: A backlight module includes a light-emitting substrate, at least one chip-on-film and a backplane. The light-emitting substrate includes a signal line group and a plurality of light-emitting units, and the plurality of light-emitting units are electrically connected to the signal line group. The at least one chip-on-film is arranged on a non-light exit side of the light-emitting substrate, and electrically connected to the signal line group. The backplane is disposed on the non-light exit side of the light-emitting substrate, and the at least one chip-on-film is located between the backplane and the light-emitting substrate. The backplane is provided with a groove therein, a notch of the groove faces the light-emitting substrate, and at least portion of a chip-on-film film of the at least one chip-on-film is disposed in the groove.
    Type: Application
    Filed: February 20, 2023
    Publication date: March 13, 2025
    Applicants: Chongqing BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yu WANG, Wencheng LUO, Meilong HU, Jinhong ZHANG, Wenqi QUAN, Wei RAN, Zhi LI, Hening ZHANG, Bowen XIONG, Qiong YUAN, Xin CEN, Ke LIAO, Yiming CHENG
  • Publication number: 20250087121
    Abstract: An detachment device for a spliced display device includes: a detachment mechanism disposed to be connected with the first display unit to drive the first display unit to move along a direction away from or close to a plane where the spliced display device is located; at least one moving device, wherein the moving device includes a moving frame located outside the detachment mechanism and an adjustment member disposed on the moving frame, the moving frame is connected with the second display unit, the adjustment member abuts against the detachment mechanism, and the moving frame drives the second display unit connected with the moving frame to move in a direction away from the first display unit through the adjustment member on the plane where the spliced display device is located.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 13, 2025
    Inventors: Wei ZHANG, Pengju HU, Yang YU, Zhenguo LI, Pengwei WANG, Junchao LU
  • Publication number: 20250086529
    Abstract: Some embodiments of the disclosure provide methods for calculating carbon footprints of leather chemical materials. In some examples, the method includes: determining a calculation range of a carbon footprint of a leather chemical material in a life cycle as “cradle to gate”; determining a system boundary, a functional unit, and cut-off criteria for the carbon footprint of the leather chemical material in the life cycle; dividing the carbon footprint into a raw chemical obtaining process, a production process of the leather chemical material, and a waste disposal process within the system boundary; determining a carbon footprint calculation model for the leather chemical material according to resource consumption and environmental emission of each process; collecting and determining a quantity and a value required by each parameter in the carbon footprint calculation model; and calculating the carbon footprint of the leather chemical material using the carbon footprint calculation model.
    Type: Application
    Filed: September 9, 2024
    Publication date: March 13, 2025
    Applicants: SICHUAN UNIVERSITY, Sichuan Chuangzhiweiye Technology Co., Ltd.
    Inventors: Jianfei ZHOU, Wei LIN, Qianchuan ZHOU, Chunhua WANG, Bi SHI, Youcheng TANG, Hexiang DONG
  • Publication number: 20250087811
    Abstract: A support assembly, a battery box, a battery, and an electric device are disclosed. The support assembly includes: at least two plate layers, where the at least two plate layers are stacked, and a separating space is provided between adjacent ones of the at least two plate layers; and a support structure disposed in the separating space, where the support structure includes a plurality of cavities, at least some of the cavities extend along a first direction, and the first direction intersects with opposite surfaces of the adjacent plate layers.
    Type: Application
    Filed: November 27, 2024
    Publication date: March 13, 2025
    Applicant: CONTEMPORARY AMPEREX TECHNOLOGY (HONG KONG) LIMITED
    Inventors: Pengbo ZHAO, Yong WANG, Ruidi LIU, Qing WANG, Wei ZHANG
  • Publication number: 20250085577
    Abstract: A display panel includes an array substrate and a color filter substrate, where the color filter substrate includes a first substrate, spacer pillars, and color filter layers, each spacer pillar is in the spacing region, and each pixel region is provided with a color filter layer. Each spacer pillar includes at least one spacer layer each made of the same material as the color filter layer in one of the pixel regions. The array substrate includes a second substrate and a support layer, where the support layer is on a side of the second substrate facing the color filter substrate, and includes a body layer and a plurality of protrusions on a side of the body layer away from the second substrate, where each protrusion is each opposite to at least one of the spacer pillars. At least one of the spacer pillars is each supported on the corresponding protrusion.
    Type: Application
    Filed: July 25, 2022
    Publication date: March 13, 2025
    Inventors: Xin ZHOU, Jiaqing LIU, Wei ZHANG, Jilei GAO, Chao LI, Liang MA, Xipeng WANG, Benzhi XU, Liangwei ZHANG, Xing ZHANG, Yonggang ZHANG
  • Publication number: 20250087611
    Abstract: An integrated device comprising a die substrate; a plurality of pads; a plurality of inner solder interconnects coupled to the plurality of pads; and a plurality of pillar shell interconnects coupled to the plurality of inner solder interconnects. The plurality of inner solder interconnects are located between the plurality of pillar shell interconnects and the plurality of pads.
    Type: Application
    Filed: September 12, 2023
    Publication date: March 13, 2025
    Inventors: Yujen CHEN, Yangyang SUN, Wei WANG
  • Publication number: 20250088981
    Abstract: This application provides a method and an apparatus for power allocation. One example method includes: A control apparatus receives capability information from a radio frequency apparatus, where the capability information indicates a correspondence between a power boost amplitude of a first channel and a power back-off amplitude of a second channel. The control apparatus sends first indication information to the radio frequency apparatus, where the first indication information indicates that the power boost amplitude of the first channel is a first amplitude and indicates that the power back-off amplitude of the second channel is a second amplitude, and the first amplitude and the second amplitude are determined based on the capability information and a required boost amplitude of the first channel.
    Type: Application
    Filed: November 25, 2024
    Publication date: March 13, 2025
    Inventor: Wei WANG
  • Publication number: 20250087888
    Abstract: An antenna assembly includes a patch antenna, a metal layer, and a feed-in signal layer. The metal layer is disposed on a side of the patch antenna and includes a first slot and a second slot. The feed-in signal layer is disposed on a side of the metal layer opposite the second antenna and includes a transmitting port, a receiving port, a hybrid coupler, and two microstrips. The transmitting port and the receiving port are connected to the hybrid coupler, and the two microstrips are extended in the direction away from the hybrid coupler. Projections of two ends of the two microstrips onto the metal layer are overlapped with the first slot and the second slot. An antenna array is also mentioned.
    Type: Application
    Filed: May 30, 2024
    Publication date: March 13, 2025
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Tse-Hsuan Wang, Chih-Fu Chang, Hsin-Feng Hsieh, Wu-Hua Chen, Chih-Wei Liao, Chao-Hsu Wu
  • Publication number: 20250087154
    Abstract: The present disclosure discloses a pixel circuit and a display panel. The pixel circuit includes a first light-emitting control transistor, a first initialization transistor, a first transistor, a light-emitting device, and a first capacitor. In the case that a reset current and a luminescent current flowing through the first light-emitting control transistor remain unchanged, the light-emitting current flowing through the light-emitting device which is a part of the luminescent current flowing through the first light-emitting control transistor is kept constant.
    Type: Application
    Filed: June 30, 2023
    Publication date: March 13, 2025
    Inventors: Wei WANG, Qing HUANG
  • Publication number: 20250089334
    Abstract: A semiconductor includes a substrate. A gate structure is disposed on the substrate. A liner oxide contacts a side of the gate structure. A silicon oxide spacer contacts the liner oxide. An end of the silicon oxide spacer forms a kink profile. A silicon nitride spacer contacts the silicon oxide spacer and a tail of the silicon nitride spacer covers part of the kink profile. A stressor covers the silicon nitride spacer and the substrate.
    Type: Application
    Filed: October 13, 2023
    Publication date: March 13, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Chen-Ming Wang, Po-Ching Su, Pei-Hsun Kao, Ti-Bin Chen, Chun-Wei Yu, Chih-Chiang Wu
  • Publication number: 20250087639
    Abstract: A method includes forming first integrated circuits on a front side of a semiconductor substrate of a first device die, forming a trench capacitor extending from a backside of the semiconductor substrate into the semiconductor substrate, and forming a first through-via and a second through-via penetrating through the semiconductor substrate. The trench capacitor is electrically coupled between the first through-via and the second through-via. A second device die is bonded to the first die. The second device die includes second integrated circuits, and power nodes of the second integrated circuits are electrically coupled to the first through-via and the second through-via.
    Type: Application
    Filed: January 2, 2024
    Publication date: March 13, 2025
    Inventors: Ke-Gang Wen, Yu-Bey Wu, Tsung-Chieh Hsiao, Liang-Wei Wang, Dian-Hau Chen
  • Publication number: 20250087627
    Abstract: A method of forming a semiconductor package includes the following operations. A first integrated circuit structure is provided, and the first integrated circuit structure includes a first substrate and a silicon layer over the first substrate. A plasma treatment is performed to transform a top portion of the silicon layer to a first bonding layer on the remaining silicon layer of the first integrated circuit structure. A second integrated circuit structure is provided, and the second integrated circuit structure includes a second substrate and a second bonding layer over the second substrate. The second integrated circuit structure is bonded to the first integrated circuit structure through the second bonding layer of the second integrated circuit structure and the first bonding layer of the first integrated circuit structure.
    Type: Application
    Filed: November 26, 2024
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chia-Wei Wang, Yu-Tzu Chang
  • Publication number: 20250088658
    Abstract: Methods and apparatuses for video coding are provided. A method includes signaling a first syntax element for determining whether information of one or more reference picture lists is present in a picture header (PH) associated with a picture; and signaling the information of the one or more reference picture lists in the PH in a case that the first syntax element has a first value, wherein in a case that the information of the one or more reference picture lists is signaled in the PH and one or more slices associated with the picture are determined, from the information of the one or more reference picture lists, as being not bi-predictive, one or more second syntax elements in the PH are not parsed.
    Type: Application
    Filed: November 25, 2024
    Publication date: March 13, 2025
    Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Yi-Wen CHEN, Xiaoyu XIU, Tsung-Chuan MA, Hong-Jheng JHU, Wei CHEN, Xianglin WANG, Bing YU
  • Patent number: 12247651
    Abstract: Embodiments of the present disclosure relate to a gearbox housing. The gearbox housing has a housing body and an annular gear. The housing body comprises an annular support and a lateral portion provided at a side face of the annular support. The lateral portion has a hole formed thereon for an input shaft to pass through. The annular gear is provided inside of the housing body along a radial direction and adapted to couple to the annular support, wherein a plurality of teeth are circumferentially provided at an inner side of the annular gear. A gear wheel with an output shaft is adapted to couple to the plurality of teeth.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: March 11, 2025
    Assignee: ABB Schweiz AG
    Inventors: Zhiqiang Tao, Hao Gu, Wei Song, Bo Qiao, Lei Wang
  • Patent number: 12248157
    Abstract: A projection screen, with a design in which the apexes of multiple triangular pyramidal units of the projection screen in an array arrangement change gradually according to a predetermined relation, an image light shone from a projector is reflected by a microstructure layer having the triangular pyramidal units and then converged in a range centered around the human eyes, so as to reduce the degree of difference in brightness at different viewing positions, thus ensuring that the projection screen is provided with excellent uniformity and high gain.
    Type: Grant
    Filed: June 28, 2020
    Date of Patent: March 11, 2025
    Assignee: APPOTRONICS CORPORATION LIMITED
    Inventors: Lin Wang, Xiaofeng Tang, Wei Sun, Yi Li
  • Patent number: 12248353
    Abstract: A method of performing power saving control on a display device includes: generating, by a timing controller of the display device, a power saving start indication and a power saving end indication in response to changing of a refresh rate of the display device; receiving, by a source driver of the display device, the power saving start indication and the power saving end indication; in response to the power saving start indication, allowing a part of circuitry of the source driver to be powered down during a vertical blanking interval; and in response to the power saving end indication, allowing the powered down part of circuitry of the source driver to be woken up during the vertical blanking interval.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: March 11, 2025
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Hung-Yu Huang, Shu-Ming Chang, Chia-Hui Wang, Shiang-Wei Wang, Sheng-Wen Huang, Tsung-Yi Tsai
  • Patent number: 12249636
    Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: March 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Hsuan Chen, Ping-Wei Wang
  • Patent number: 12249383
    Abstract: A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: March 11, 2025
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Wei Yan, Zhen Wang, Wenwen Qin, Han Zhang, Deshuai Wang, Jian Zhang, Yue Shan, Xiaoyan Yang, Yadong Zhang, Jian Sun
  • Patent number: 12248807
    Abstract: Techniques for migration of a source protected virtual machine from a source platform to a destination platform are descried. A method of an aspect includes enforcing that bundles of state, of a first protected virtual machine (VM), received at a second platform over a stream, during an in-order phase of a migration of the first protected VM from a first platform to the second platform, are imported to a second protected VM of the second platform, in a same order that they were exported from the first protected VM. Receiving a marker over the stream marking an end of the in-order phase. Determining that all bundles of state exported from the first protected VM prior to export of the marker have been imported to the second protected VM. Starting an out-of-order phase of the migration based on the determination that said all bundles of the state exported have been imported.
    Type: Grant
    Filed: December 26, 2020
    Date of Patent: March 11, 2025
    Assignee: Intel Corporation
    Inventors: Ravi Sahita, Dror Caspi, Vincent Scarlata, Sharon Yaniv, Baruch Chaikin, Vedvyas Shanbhogue, Jun Nakajima, Arumugam Thiyagarajah, Sean Christopherson, Haidong Xia, Vinay Awasthi, Isaku Yamahata, Wei Wang, Thomas Adelmeyer