Abstract: Methods for reducing contact resistance include performing a selective titanium silicide (TiSi) deposition process on a middle of the line (MOL) contact structure that includes a cavity in a substrate of dielectric material. The contact structure also includes a silicon-based connection portion at a bottom of the cavity. The selective TiSi deposition process is selective to silicon-based material over dielectric material. The methods also include performing a selective deposition process of a metal material on the MOL contact structure. The selective deposition process is selective to TiSi material over dielectric material and forms a silicide capping layer on the silicon-based connection portion. The methods further include performing a seed layer deposition process of the metal material on the contact structure.

Abstract: The present disclosure is directed to compounds of Formula (1): wherein m, n, Y, R1, R2, R3, R4 and R5 are each as described herein, as stereoisomers, enantiomers or tautomers thereof or mixtures thereof; or pharmaceutically acceptable salts, solvates or prodrugs thereof, and pharmaceutical compositions comprising the compounds of Formula (I), as described herein, which are useful as voltage-gated potassium channel modulators and are therefore are useful in treating seizure disorders such as epilepsy.

Abstract: The present disclosure relates to antibodies that bind human LAIR1 (“anti-human LAIR1 antibodies” or “anti-human LAIR1 antibodies”), compositions comprising such anti-human LAIR1 antibodies, and methods of using such anti-human LAIR1 antibodies.

Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.

Abstract: A charging port device includes a charging port driver, a fast charging driver, a slow charging driver, a slow charging port cover, a fast charging port cover, an outer cover, and a mounting housing provided with a mounting hole. A fast charging port and a slow charging port are arranged in the mounting hole. An output terminal of the charging port driver is connected with the outer cover, and the outer cover is configured to cover the mounting hole. An output terminal of the fast charging driver is connected with the fast charging port cover, and the fast charging port cover is configured to cover the fast charging port. An output terminal of the slow charging driver is connected with the slow charging port cover, and the slow charging port cover is configured to cover the slow charging port.

Abstract: A condensing heat exchanger (100) capable of lowering a requirement for a fan and a water heater having the same, wherein the condensing heat exchanger (100) comprises: a heat exchanger housing (110) having a flue gas inlet (101) and a flue gas outlet (102); and a heat exchange unit (104) located within the heat exchanger housing (110), wherein a sidewall flue gas exhaust channel (105) communicated with the flue gas outlet (102) is provided between the heat exchange unit (104) and an inner sidewall of the heat exchanger housing (110), the heat exchange unit (104) surrounds a flue gas inlet channel (103) communicated with the flue gas inlet (101), the sidewall flue gas exhaust channel (105) surrounds the heat exchange unit (104), and the heat exchange unit (104) is internally provided with a heat exchange flue which communicates the flue gas inlet channel (103) with the sidewall flue gas exhaust channel (105).

Abstract: The present disclosure provides a direct current (DC) transformer error detection apparatus for a pulsating harmonic signal, including a DC and pulsating harmonic current output module and an external detected input module, where the DC and pulsating harmonic current output module outputs a DC and a DC superimposed pulsating harmonic current to an internal sampling circuit and a self-calibrated standard resistor array; and the internal sampling circuit converts the input DC and the input DC superimposed pulsating harmonic current into a voltage signal, and sends the voltage signal to an analog-to-digital (AD) sampling and measurement component through a front-end conditioning circuit and a detected input channel. The DC transformer error detection apparatus can complete self-calibration for measurement of the DC and the pulsating harmonic signal on a test site.

Abstract: A data bus coupled to a plurality of memory devices is determined to be in a read mode. Responsive to determining that the data bus is in the read mode, a particular read operation identified in a particular memory queue of memory queues that include identifiers of one or more write operations and identifiers of one or more read operations is determined. The particular memory queue includes a highest number of read operations for a memory device of the memory devices. The particular read operation is transmitted from the particular memory queue over the data bus.

Abstract: The embodiment of the present disclosure discloses a method, an electronic device, and a storage medium for a ship route optimization. The method for the ship route optimization considers a dynamic feature of a multi-functional emergency rescue ship and an interference effect caused by an airflow, uses a movement model with kinematics non-holonomic constraints, such as a ship total cost assessment function to simulate the movement of the ship, and based on a sparrow search algorithm, learns how to apply the algorithm to a route plan of the emergency rescue ship. The method can improve the ship route optimization algorithm, improve an accuracy and practical applicability of a calculated plan. The method can effectively and accurately locate obstacles and hidden reefs, and consider effects of an airflow and a non-holonomic constraint effect, so as to make the route planning of the ship more efficient and intelligent.

Abstract: A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

Abstract: Systems, methods, and apparatuses relating to interlocking transistor active regions are disclosed. An apparatus includes a gate including electrically conductive material and an active material including a doped semiconductor material. A portion of the active material overlapped by the gate has an at least substantially triangular shape. An apparatus includes a plurality of active materials. Each active material includes tapered ends and a plurality of gates. The plurality of active materials is arranged in an interlocking pattern with at least some tapered ends of the active materials interlocking with at least some others of the tapered ends. The plurality of gates overlaps the interlocked tapered ends of the plurality of active materials.

Abstract: A laminating device includes: a plate being bendable, having a resilience characteristic and for bearing the flexible substrate; a supporting base platform for supporting the plate and driving the plate and the flexible substrate on the plate to move; a bending assembly for applying stress to drive the plate and the flexible substrate on the plate to be bent towards a side, facing away from the flexible substrate, of the plate, and for releasing stress to allow the plate and the flexible substrate to rebound; and a fixing fixture for fixing the protective cover plate. The protective cover plate is used to be laminated to the flexible substrate, a shape of the fixing fixture is same as or similar to that of the protective cover plate, the fixing fixture is bent to form an accommodating space, and the protective cover plate is fixed in the accommodating space.

Abstract: Described herein are systems and techniques for monitoring for monitoring and evaluating conditions associated with a wellbore and wellbore operations that use neural operators instead of computationally intensive iterative differential equations. Such systems and techniques allow for determinations to be made as operations associated with a wellbore are performed. Instead of having to wait for computationally intensive tasks to be performed or take risks of proceeding with a wellbore operation without real-time evaluations being performed, these wellbore operations may be continued while determinations are timely made, thus improving operation of computing systems that perform evaluations and that make decisions regarding safely and efficiently performing wellbore operations such as drilling a wellbore, cementing wellbore casings in place, or injecting fluids into formations of the Earth.

Abstract: A touch structure and a display panel are provided. The touch structure includes: first mesh electrodes extending in a first direction and second mesh electrodes extending in a second direction. The touch structure is absent in a window region. First mesh electrodes include at least one cross-window row separated by the window region, which includes a first cross-window row including: a first window mesh block adjacent to the window region and on a first side of the window region; a first conductive plate directly connected to mesh lines of the first window mesh block; and a first non-window mesh block on a side of the first window mesh block away from the window region; second mesh electrodes include at least one cross-window column including a first cross-window column which includes: a second window mesh block; a second conductive plate; and a second non-window mesh block.

Abstract: Provided is an unbalanced sample data preprocessing method, which includes: a data acquisition request is received and initial data is acquired according to the data acquisition request, and the initial data is classified according to a preset classification rule to obtain first-class sample sets and second-class sample sets; characteristics of K first sample points extracted are analyzed to obtain a new data characteristic of the first-class sample sets; a new data label of the first-class sample sets is generated according to a first label corresponding to the first-class sample sets; a ratio between the number of first-class sample sets and the number of second-class sample sets is calculated; and new data of the first-class sample sets is generated according to the new data characteristic and the new data label, and the amount of new data is adjusted according to the ratio to increase the number of first-class sample sets.

Abstract: A system for determining a location of a feature of an object, the system including a first marker including a first area and a surface having two parallel edges and a third edge disposed perpendicularly to the two parallel edges, the two parallel edges are disposed about a first central axis of the two parallel edges; and a sensor configured to provide a distance from the sensor to a portion of the first marker, wherein the sensor is adapted to obtain distances between the sensor and the first marker and an environment surrounding the first marker to form a first map representing the distances corresponding to locations from which the distances are obtained using the sensor and the location of the feature of the object is determined based on at least one corner corresponding to an intersection formed of the third edge and one of the two parallel edges.

Abstract: An operation method of a network device and a control chip of the network device are provided. The network device receives an input signal through a fiber medium. The operation method includes the following steps: setting a target speed of the network device to a first speed; transmitting and/or receiving a data at the first speed; and setting the target speed of the network device to a second speed which is different from the first speed when the amplitude or energy of the input signal is not greater than a threshold.

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: A semiconductor device includes a substrate, at least one via, a liner layer and a conductive layer. The substrate includes an electronic circuitry. The at least one via passes through the substrate. The at least one via includes a plurality of concave portions on a sidewall thereof. The liner layer fills in the plurality of concave portions of the at least one via. The conductive layer is disposed on the sidewall of the at least one via, covers the liner layer, and extends onto a surface of the substrate. The thickness of the conductive layer on the sidewall of the at least one via is varied.