Patents by Inventor Wei Yeh

Wei Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240052241
    Abstract: A semiconductor quantum dot structure includes a core and a shell. The core includes a seed crystal made of a first compound M1C1, a core layer, and a barrier layer grown in such order. The seed crystal has first regions that are inactive with oxygen, and second regions that are easily reactive with oxygen. The core layer is made of the first compound M1C1, and has first and second areas. Each of the first areas is positioned on a corresponding one of the first regions. Each of the second areas is positioned on a corresponding one of the second regions. Each of the first areas has a thickness greater than that of each of the second areas. The barrier layer is made of a second compound selected from M1X1 and X2C1. The shell is grown on the barrier layer, and is made of a third compound M2C2.
    Type: Application
    Filed: February 14, 2023
    Publication date: February 15, 2024
    Inventors: Chang-Wei YEH, Hsueh-Shih CHEN, Cheng-Yang CHEN
  • Publication number: 20240053885
    Abstract: An electronic apparatus and a hotkey prompt method thereof are provided. The method includes the following steps. A power-on self-test (POST) procedure of a basic input output system (BIOS) is performed. During the POST procedure, a display panel of a keyboard module is controlled to display a first keyboard layout, so as to display at least one hotkey corresponding to at least one hotkey function of the BIOS via the display panel. After a hotkey input operation is received via the keyboard, a first hotkey function of the at least one hotkey function of the BIOS is performed. The hotkey input operation is used to enable the first hotkey function. In response to performing the first hotkey function, the display panel of the keyboard module is controlled to display a second keyboard layout.
    Type: Application
    Filed: December 14, 2022
    Publication date: February 15, 2024
    Applicant: Acer Incorporated
    Inventor: Shu-Wei Yeh
  • Publication number: 20240047581
    Abstract: A semiconductor structure includes a semiconductor substrate, a gate electrode, a first spacer, and a first contact etch stop layer (CESL). The semiconductor substrate includes a fin structure. The gate electrode is over the fin structure. The first spacer is over the fin structure and on a lateral side of the gate electrode, wherein a top surface of the first spacer is inclined towards the gate electrode. The first CESL is over the fin structure and contacting the first spacer, wherein an angle between the top surface of the first spacer and a sidewall of the first CESL is less than about 140°.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 8, 2024
    Inventors: SHAO-HUA HSU, CHIH-WEI WU, MAO-LIN WENG, WEI-YEH TANG, YEN-CHENG LAI, CHUN-CHAN HSIAO, PO-HSIANG CHUANG, CHIH-LONG CHIANG, YIH-ANN LIN, RYAN CHIA-JEN CHEN
  • Publication number: 20240038978
    Abstract: The present invention provides a titanium-niobium composite oxide, which includes titanium, niobium, dopant M and oxygen, and the molar ratio of the titanium, niobium and dopant M is 1:(2?x):x, and x is 0.01 to 0.2; wherein the dopant M is doped in a crystal structure with a monoclinic crystal structure formed from the titanium, niobium and oxygen, and the dopant M is at least one metal element selected from the group consisting of Sn, Al and Zr. The present invention further provides a preparation method of the titanium-niobium composite oxide, an active material and a lithium ion secondary battery using the same. The titanium-niobium composite oxide produced by the present invention has better electrical performance than the existing negative electrode materials, so that the lithium ion secondary battery using it can exhibit longer cycle life, larger electric capacity and faster charging and discharging performance, thereby having a bright prospect of the application.
    Type: Application
    Filed: February 6, 2023
    Publication date: February 1, 2024
    Applicant: GUS TECHNOLOGY CO., LTD.
    Inventors: Chung-Chieh CHANG, Kuo-Wei YEH, Wen-Chia HSU, Jia-Hui WANG, Chia-Huan CHUNG, Dong-Ze WU, PREM CHANDAN DEVANGA
  • Publication number: 20240022440
    Abstract: In a blockchain system, a user device obtains an address of a smart contract according to a transaction hash, and generates a private data hash according to business data. The user device then generates a transaction based on the private data hash and the address of the smart contract, and submits the transaction to the blockchain system to store the private data hash into the smart contract, such that confidential information of a business deal in the real world is secured. An authentication device generates a private data hash according to business data, obtains an address of a smart contract in the blockchain system according to a transaction hash, and accesses the smart contract via the address to determine whether the private data hash is stored in the smart contract. The authentication device approves the business data when the smart contract includes the private data hash.
    Type: Application
    Filed: July 18, 2022
    Publication date: January 18, 2024
    Inventor: Wei YEH
  • Publication number: 20240023357
    Abstract: A quantum dot includes a nanocrystalline core and a nanocrystalline shell. The nanocrystalline core includes a core body and a doping material that is non-uniformly doped in the core body. The core body has a sphalerite-type crystal structure, and includes at least one element from Group IB, at least one element from Group IIIA and at least one element from Group VIA. The doping material includes at least one doping element selected from the group consisting of an element from Group IB, an element from Group IIB and an element from Group IIIA. The nanocrystalline shell surrounds the nanocrystalline core and includes at least one element from Group VIA, and at least one element from one of Group IIB and Group IIIA. A method for preparing the quantum dot is also disclosed.
    Type: Application
    Filed: December 20, 2022
    Publication date: January 18, 2024
    Inventors: Chang-Wei YEH, Hsueh-Shih CHEN, Yuan CHEN
  • Patent number: 11864391
    Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).
    Type: Grant
    Filed: December 26, 2022
    Date of Patent: January 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Te-Wei Yeh, Chien-Liang Wu
  • Patent number: 11859237
    Abstract: A method for sizing a DNA molecule is disclosed, which comprises the following steps of: providing a DNA sizing device, comprising: a cover substrate; a substrate disposed on the cover substrate and comprising a first hole and a second hole; and a first slit-like channel disposed between the cover substrate and the substrate, wherein two ends of the first slit-like channel respectively connects to the first hole and the second hole; loading a sample comprising a DNA molecule to the first slit-like channel through the first hole, wherein the DNA molecule moves in a direction from the first hole to the second hole; detecting and recording an intensity and an area of a distribution of the DNA molecule; and analyzing the intensity and the area to obtain the size of a DNA molecule.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 2, 2024
    Assignee: ACADEMIA SINICA
    Inventors: Chia-Fu Chou, Jia-Wei Yeh, Yii-Lih Lin
  • Patent number: 11862842
    Abstract: Provided is a display apparatus including a display panel, multiple antenna electrodes, a dummy electrode, and multiple feed lines. The display panel has a display area. The antenna electrodes are disposed on the display panel and overlap the display area. The dummy electrode is disposed around the antenna electrodes and overlaps the display area. The dummy electrode is electrically separated from the antenna electrodes, and has multiple dummy wire segments whose extension directions intersect each other. The dummy wire segments have multiple breaks. The feed lines are respectively electrically connected to the antenna electrodes. An antenna module is also provided.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: January 2, 2024
    Assignee: Au Optronics Corporation
    Inventors: Chen-Yi Chang, Chao-Wei Yeh, Yu-Ling Yeh, Pei-Heng Li, Chao-Yang Chou, Hsi-Tseng Chou
  • Patent number: 11854632
    Abstract: A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: December 26, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Chien-Liang Wu, Wen-Kai Lin, Te-Wei Yeh, Sheng-Yuan Hsueh, Chi-Horn Pai
  • Patent number: 11854471
    Abstract: The present disclosure provides a method for a display driver system and a display driver system.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: December 26, 2023
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Hsu-Chih Wei, Po-Hsiang Fang, Keko-Chun Liang, Che-Wei Yeh, Ju-Lin Huang
  • Publication number: 20230395426
    Abstract: Provided is a conductive structure and a method for forming such a structure. The method includes forming a treatable layer by depositing a layer comprising a metal over a structure; performing a directional treatment process on a targeted portion of the treatable layer to convert the targeted portion to a material different from a non-targeted portion of the treatable layer, wherein the directional treatment process is selected from the group consisting of nitridation, oxidation, chlorination, carbonization; and selectively removing the non-targeted portion from the structure, wherein the targeted portion remains over the structure.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiang Chao, Shu-Lan Chang, Ching-Yi Chen, Shih-Wei Yeh, Pei Shan Chang, Ya-Yi Cheng, Yu-Chen Ko, Yu-Shiuan Wang, Chun-Hsien Huang, Hung-Chang Hsu, Chih-Wei Chang, Ming-Hsing Tsai, Wei-Jung Lin
  • Publication number: 20230371668
    Abstract: A contact lens packaging container and a contact lens product are provided. The contact lens packaging container is formed by a plastic material and a color powder material dispersed in the plastic material. The contact lens packaging container has a light blocking rate of not less than 20% under a wavelength measurement range between 380 nanometers and 780 nanometers through a spectrophotometer.
    Type: Application
    Filed: September 15, 2022
    Publication date: November 23, 2023
    Inventors: TSUNG-YANG LEE, WEI-AN YEH
  • Patent number: 11824966
    Abstract: A transmitter is configured to transmit a series of command signals and a series of data signals. The transmitter includes a serializer and a multiplexer. The serializer is configured to generate the series of data signals. The multiplexer, coupled to the serializer, is configured to selectively output the series of command signals or the series of data signals.
    Type: Grant
    Filed: January 31, 2021
    Date of Patent: November 21, 2023
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Yong-Ren Fang, Yu-Hsiang Wang, Che-Wei Yeh
  • Publication number: 20230360969
    Abstract: A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.
    Type: Application
    Filed: May 6, 2022
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Ting Chung, Shih-Wei Yeh, Kai-Chieh Yang, Yu-Ting Wen, Yu-Chen Ko, Ya-Yi Cheng, Min-Hsiu Hung, Chun-Hsien Huang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 11790822
    Abstract: A display apparatus is provided. The display apparatus includes a display panel and a plurality of flexible printed circuit boards. The display panel has a fan-out area and a display area. The flexible printed circuit boards are coupled to the display panel. A first side of each flexible printed circuit board is configured with a plurality of first traces for transmitting a first group of clock signals among a plurality of clock signals, and a second side of each flexible printed circuit board opposite to the first side is configured with a plurality of second traces for transmitting a second group of clock signals among the clock signals. The first group of clock signals of one of the flexible printed circuit boards and the second group of clock signals of the adjacent flexible printed circuit board are transmitted to the display area through the fan-out area together.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: October 17, 2023
    Assignee: AUO Corporation
    Inventors: Yen-Wei Yeh, Wei-Li Lin
  • Patent number: 11784437
    Abstract: A card connector includes a transmission conductor assembly that includes a backup transmission conductor, a first signal transmission conductor, an inspection signal transmission conductor, a first grounding transmission conductor, a command reset transmission conductor, a first differential transmission conductor, a second differential transmission conductor, a second grounding transmission conductor, a third grounding transmission conductor, a fourth grounding transmission conductor, a first power transmission conductor, a second power transmission conductor, a third differential transmission conductor, a fourth differential transmission conductor, a second signal transmission conductor, a fifth grounding transmission conductor, a sixth grounding transmission conductor, a seventh grounding transmission conductor, a fifth differential transmission conductor, a sixth differential transmission conductor, and a write-protection transmission conductor, each of which has two ends respectively forming a spring se
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: October 10, 2023
    Assignee: V-GENERAL TECHNOLOGY CO., LTD.
    Inventors: Po-Wen Yeh, Hsuan Ho Chung, Yung-Chang Lin, Yu Hung Lin, Tzu-Wei Yeh, Yu-Lun Yeh
  • Patent number: 11767578
    Abstract: A high strength and wear resistant multi-element copper alloy is disclosed. The multi-element copper alloy comprises: 80-90 atomic percent Cu, 0.1-4 atomic percent Al, 6-10 atomic percent Ni, 0.1-3 atomic percent Si, 0.1-2 atomic percent V and/or Nb, and 0.1-2 atomic percent M. Experimental data reveal that, after being applied with an aging treatment under 450 degrees Celsius for 50 hours, hardness and strength of the multi-element copper alloy are both significantly enhanced because of age hardening, and softening due to overaging is not observed on the multi-element copper alloy. Moreover, measurement data have indicated that, this novel multi-element copper alloy exhibits better wear resistance superior to that of the conventional copper alloys.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: September 26, 2023
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventor: Jien-Wei Yeh
  • Publication number: 20230295639
    Abstract: Polypeptide are disclosed that comprise an amino acid sequence at least 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 91%, 92%, 93%, 94%, 95%, 96%, 97%, 98%, 99%, or 100% identical to the amino acid sequence selected from the group consisting of SEQ ID NO:1-1615, not including any functional domains added fused to the protein (whether N-terminal, C-terminal, or internal), and wherein the 1, 2, 3, 4, or 5 N-terminal and/or C-terminal amino acid residues may be present or absent when considering the percent identity.
    Type: Application
    Filed: January 17, 2023
    Publication date: September 21, 2023
    Inventors: Christoffer NORN, Ivan ANISHCHANKA, David BAKER, Sam PELLOCK, Douglas TISCHER, Hsien-Wei YEH
  • Patent number: 11765891
    Abstract: A one-time programmable (OTP) memory cell includes a substrate having a first conductivity type and having an active area surrounded by an isolation region, a transistor disposed on the active area, and a capacitor disposed on the active area and electrically coupled to the transistor. The capacitor comprises a diffusion region of a second conductivity type in the substrate, a metallic film in direct contact with the active area, a capacitor dielectric layer on the metallic film, and a metal gate surrounded by the capacitor dielectric layer. The diffusion region and the metallic film constitute a capacitor bottom plate.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: September 19, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chun-Hsien Lin, Yung-Chen Chiu, Chien-Liang Wu, Te-Wei Yeh