Patents by Inventor Wei Yin

Wei Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230027789
    Abstract: Improved gate structures, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; a gate electrode over the high-k dielectric layer; a conductive cap over and in contact with the high-k dielectric layer and the gate electrode, a top surface of the conductive cap being convex; and first gate spacers on opposite sides of the gate structure, the high-k dielectric layer and the conductive cap extending between opposite sidewalls of the first gate spacers.
    Type: Application
    Filed: April 27, 2022
    Publication date: January 26, 2023
    Inventors: Li-Wei Yin, Yun-Chen Wu, Tzu-Wen Pan, Jih-Sheng Yang, Yu-Hsien Lin, Ryan Chia-Jen Chen
  • Publication number: 20220384269
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Patent number: 11502076
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Publication number: 20220298242
    Abstract: The present invention provides an anti-CD3 single chain Fab molecule and an anti-CD20 single chain Fab molecule and their use in preparation of a bispecific antibody. The present invention also provides a bispecific antibody targeting CD3 and CD20 and its use in preparation of a medicament for treatment of a B-cell related disease.
    Type: Application
    Filed: July 23, 2020
    Publication date: September 22, 2022
    Inventors: Yang Yang, Wei Yin
  • Publication number: 20220303718
    Abstract: The present disclosure relates to an edge system. The edge system includes a plurality of first-layer circles and a second-layer circle, and a geographical area represented by the second-layer circle includes a geographical area represented by each first-layer circle, that is, the plurality of first-layer circles are deployed in the second-layer circle. Each first-layer circle includes a plurality of sites, the plurality of sites include an initial site and are also included in the second-layer circle, and the initial site processes a data operation request sent by a client in a first-layer circle including the initial site, and in the second-layer circle. The edge system implements more secure and efficient data processing.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 22, 2022
    Inventor: Wei Yin
  • Patent number: 11443481
    Abstract: This disclosure describes implementations of a three-dimensional (3D) scene recovery system that reconstructs a 3D scene representation of a scene portrayed in a single digital image. For instance, the 3D scene recovery system trains and utilizes a 3D point cloud model to recover accurate intrinsic camera parameters from a depth map of the digital image. Additionally, the 3D point cloud model may include multiple neural networks that target specific intrinsic camera parameters. For example, the 3D point cloud model may include a depth 3D point cloud neural network that recovers the depth shift as well as include a focal length 3D point cloud neural network that recovers the camera focal length. Further, the 3D scene recovery system may utilize the recovered intrinsic camera parameters to transform the single digital image into an accurate and realistic 3D scene representation, such as a 3D point cloud.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 13, 2022
    Assignee: Adobe Inc.
    Inventors: Wei Yin, Jianming Zhang, Oliver Wang, Simon Niklaus, Mai Long, Su Chen
  • Publication number: 20220284613
    Abstract: This disclosure describes one or more implementations of a depth prediction system that generates accurate depth images from single input digital images. In one or more implementations, the depth prediction system enforces different sets of loss functions across mix-data sources to generate a multi-branch architecture depth prediction model. For instance, in one or more implementations, the depth prediction model utilizes different data sources having different granularities of ground truth depth data to robustly train a depth prediction model. Further, given the different ground truth depth data granularities from the different data sources, the depth prediction model enforces different combinations of loss functions including an image-level normalized regression loss function and/or a pair-wise normal loss among other loss functions.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 8, 2022
    Inventors: Wei Yin, Jianming Zhang, Oliver Wang, Simon Niklaus, Mai Long, Su Chen
  • Publication number: 20220277514
    Abstract: This disclosure describes implementations of a three-dimensional (3D) scene recovery system that reconstructs a 3D scene representation of a scene portrayed in a single digital image. For instance, the 3D scene recovery system trains and utilizes a 3D point cloud model to recover accurate intrinsic camera parameters from a depth map of the digital image. Additionally, the 3D point cloud model may include multiple neural networks that target specific intrinsic camera parameters. For example, the 3D point cloud model may include a depth 3D point cloud neural network that recovers the depth shift as well as include a focal length 3D point cloud neural network that recovers the camera focal length. Further, the 3D scene recovery system may utilize the recovered intrinsic camera parameters to transform the single digital image into an accurate and realistic 3D scene representation, such as a 3D point cloud.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Wei Yin, Jianming Zhang, Oliver Wang, Simon Niklaus, Mai Long, Su Chen
  • Patent number: 11416200
    Abstract: The disclosure relates to a display method and a display system. The display method includes: connecting a plurality of display devices in series with each other, the plurality of display devices including a main display device and at least one slave display device, the main display device having EDID; setting the connection order of the display device; correspondingly changing the EDID of the main display device according to the connection order of the display device; configuring the main display device to receive the display image according to the changed EDID; and configuring the display device to perform an image segmentation operation on the display image according to the connection order to respectively display multiple segmented regions of the display image.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: August 16, 2022
    Assignee: Optoma Corporation
    Inventors: Wei-Wei Yin, Jui-Chi Chen, Yen-Hsiang Hung
  • Publication number: 20220221270
    Abstract: A calibration method for fringe projection systems based on plane mirrors. Firstly, two mirrors are placed behind the tested object. Through the reflection of mirrors, the camera can image the measured object from the front and other two perspectives, so as to obtain 360-degree two-dimensional information of the measured object. The projector projects three sets of phase-shifting fringe patterns with frequencies of 1, 8, and 64. The camera captures the fringe image to obtain an absolute phase map with a frequency of 64 by using the phase-shifting method and the temporal phase unwrapping algorithm. By using the calibration parameters between the projector and the camera, the absolute phase map can be converted into three-dimensional information of the measured object. Then, the mirror calibration is realized by capturing a set of 3D feature point pairs, so that the 3D information from different perspectives is transformed into a unified world coordinate system.
    Type: Application
    Filed: August 7, 2020
    Publication date: July 14, 2022
    Applicant: Nanjing University of Science and Technology
    Inventors: Chao Zuo, Wei Yin, Qian Chen, Shijie Feng, Jiasong Sun, Tianyang Tao, Yan Hu, Liang Zhang, Jiaming Qian
  • Patent number: 11382921
    Abstract: Disclosed is a use of 5?-androstane-3?,5,6?-triol, an analogue, a deuterated derivative, and a pharmaceutically acceptable salt thereof in manufacture of a medicament for the treatment of hemorrhagic stroke in a patient. The hemorrhagic stroke is intracerebral hemorrhage or subarachnoid hemorrhage.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: July 12, 2022
    Assignee: GUANGZHOU CELLPROTEK PHARMACEUTICAL CO., LTD
    Inventors: Guangmei Yan, Yijun Huang, Wei Yin, Suizhen Lin
  • Publication number: 20220215002
    Abstract: This application discloses an image file management method, including: receiving a write instruction used to instruct to write a first image file; determining, based on the write instruction, at least one first edge cloud node from a plurality of edge cloud nodes included in an image file management system; and writing a plurality of data blocks included in the first image file into the at least one first edge cloud node, so that each first edge cloud node stores a part or all of the plurality of data blocks included in the first image file. In this application, time overheads for downloading an image file are reduced, and a download speed of the image file is improved.
    Type: Application
    Filed: March 25, 2022
    Publication date: July 7, 2022
    Inventors: Rui Luo, Wei Yin
  • Publication number: 20220059685
    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding higher than top surfaces of isolation regions. The isolation regions include a portion between the first and the second semiconductor fins. The method further includes forming a gate stack crossing over the first and the second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation regions, the first semiconductor fin, and the second semiconductor fin are exposed to the opening, etching the first semiconductor fin, the second semiconductor fin, and the portion of the isolation regions to extend the opening into a bulk portion of a semiconductor substrate below the isolation regions, and filling the opening with a dielectric material to form a cut-fin isolation region.
    Type: Application
    Filed: November 8, 2021
    Publication date: February 24, 2022
    Inventors: Shiang-Bau Wang, Li-Wei Yin, Shao-Hua Hsu
  • Patent number: 11234968
    Abstract: The present invention belongs to the field of biomedicine and relates to use of VCP (valosin-containing protein, VCP) inhibitor and oncolytic virus in the preparation of an anti-tumor drug. The present invention firstly discovers that VCP inhibitor can be used in the preparation of an anti-tumor synergist for oncolytic virus. Meanwhile, the present invention relates to a pharmaceutical composition comprising VCP inhibitor and oncolytic virus, a pharmaceutical kit comprising VCP inhibitor and oncolytic virus, and use of VCP inhibitor and oncolytic virus for treating tumor, especially a tumor that is not sensitive to oncolytic virus. The present invention also relates to an anti-tumor administration system, characterized in that, comprising oncolytic virus and a reagent for detecting the expression level of VCP.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: February 1, 2022
    Assignee: Guangzhou Virotech Pharmaceutical Co., Ltd.
    Inventors: Guangmei Yan, Haipeng Zhang, Yuan Lin, Suizhen Lin, Jing Cai, Shoufang Gong, Jun Hu, Xiao Xiao, Kai Li, Jiankai Liang, Yaqian Tan, Wenbo Zhu, Wei Yin
  • Patent number: 11233395
    Abstract: Disclosed are a dynamic lightning protection method and system. The method includes detecting lightning in real time and tracking a position of a thunderstorm; and performing dynamic lightning protection and control on an electrical grid according to an electrical grid control strategy before the thunderstorm reaches or affects the electrical grid. Further disclosed is a dynamic lightning protection system.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: January 25, 2022
    Assignees: STATE GRID JIANGSU ELECTRIC POWER CO., LTD SUZHOU, STATE GRID JIANGSU ELECTRIC POWER CO., LTD, STATE GRID CORPORATION OF CHINA
    Inventors: Chong Tong, Yunfeng Cai, Ziyang Zhang, Qing Wang, Kang Dai, Wei Yin
  • Publication number: 20210351084
    Abstract: In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 11, 2021
    Inventors: Shiang-Bau Wang, Li-Wei Yin, Chen-Huang Huang, Ming-Jhe Sie, Ryan Chia-Jen Chen
  • Patent number: 11171236
    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding higher than top surfaces of isolation regions. The isolation regions include a portion between the first and the second semiconductor fins. The method further includes forming a gate stack crossing over the first and the second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation regions, the first semiconductor fin, and the second semiconductor fin are exposed to the opening, etching the first semiconductor fin, the second semiconductor fin, and the portion of the isolation regions to extend the opening into a bulk portion of a semiconductor substrate below the isolation regions, and filling the opening with a dielectric material to form a cut-fin isolation region.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiang-Bau Wang, Li-Wei Yin, Shao-Hua Hsu
  • Publication number: 20210280695
    Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.
    Type: Application
    Filed: May 20, 2021
    Publication date: September 9, 2021
    Inventors: Ryan Chia-Jen Chen, Li-Wei Yin, Tzu-Wen Pan, Cheng-Chung Chang, Shao-Hua Hsu, Yi-Chun Chen, Yu-Hsien Lin, Ming-Ching Chang
  • Patent number: 11114549
    Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ryan Chia-Jen Chen, Ming-Ching Chang, Yi-Chun Chen, Yu-Hsien Lin, Li-Wei Yin, Tzu-Wen Pan, Cheng-Chung Chang, Shao-Hua Hsu
  • Patent number: D939469
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: December 28, 2021
    Inventors: Wei Yin, Yong Xu, Ningning Li, Zhiyao Wang, Tao Wang