Abstract: A method of fabricating a borderless via is disclosed. A semiconductor substrate having a first dielectric layer thereon is provided. Next, a first conductive structure and a second conductive structure whose area is much smaller than said first conductive structure are formed on said first dielectric layer. After that, a second dielectric layer with an uneven surface is formed. Then, a planarizing layer is coated over said second dielectric layer to fill said uneven surface. Next, an etch back process is used to create a etching stop layer consisting of a portion of second dielectric layer. Subsequently, a third dielectric layer is formed over said second dielectric layer followed by selectively etching said third dielectric layer until said second dielectric layer is exposed to create a borderless via.

Abstract: A method for forming a pullback opening above a shallow trench isolation structure. A patterned mask layer is formed over a substrate. A sacrificial layer is formed on the sidewalls of the mask layer. The exposed portion of the substrate is etched to form a trench in the substrate. The sacrificial layer is removed to increase the width of the opening above the trench.

Abstract: A fitting includes a stem extending in an axial direction and having a threaded surface adapted to be screwed into an upright wall. An annular head portion is connected to the stem, and has an abutting surface wall proximate to the stem and extending in a transverse direction relative to the axial direction for abutting against the upright wall when the stem is fixed in the upright wall. A cylindrical anchored member extends from the head portion in the axial direction away from the stem, and has a distal end distal to the abutting surface wall. A holding member includes an anchoring portion which is elongated in the axial direction to be sleeved on and to cover the anchored member, and a holding portion which is formed integrally with the anchoring portion for holding a support member. A fastening member is disposed to fix the anchoring portion relative to the anchored member by tightening along a radial direction relative to the axial direction.

Abstract: A double recess crown-shaped DRAM capacitor is formed in a simplified process. A dielectric layer is formed over a substrate. Using photolithographic and etching techniques, a contact opening is formed in the dielectric layer. A conductive layer is formed over the dielectric layer filling the contact opening to form a conductive plug. A second dielectric layer is formed over the conductive layer. Again using photolithographic and etching techniques, the second dielectric layer is patterned to form a trapezoidal-shaped dielectric layer. An organic bottom anti-reflective coating (organic BARC) is coated over the trapezoidal-shaped dielectric layer and the conductive layer. Organic BARC above the trapezoidal-shaped dielectric layer is removed. Using the organic BARC as an etching mask, the trapezoidal-shaped dielectric layer is etched to form triangular-shaped dielectric layers and a trench in the conductive layer. The residual organic BARC is completely removed.

Abstract: A method of manufacturing a DRAM capacitor is described. A silicon substrate structure includes an oxide layer over a substrate and a polysilicon layer over the oxide layer. The polysilicon layer also includes a plug that penetrates the oxide layer. A patterned photoresist layer is next formed over the polysilicon layer. Spacers having a low etching rate are formed on the sidewalls of the photoresist layer by carrying out a chemical reaction next to the sidewall of the photoresist layer. A dry etching operation is carried out to etch the unreacted photoresist layer and the polysilicon layer exposed by the openings in the photoresist layer. Using the spacers as an etching mask, a portion of the polysilicon layer under the photoresist layer is removed by continuing the dry etching operation. Lastly, the spacers are removed to form a crown-shaped capacitor.

Abstract: The present invention discloses a method for forming hard mask of half critical dimension on a substrate. A substrate is provided for the base of integrated circuits. A silicon oxide layer is formed on the substrate. A photoresist layer is formed on the silicon oxide layer and it is has a critical dimension, which the conventional lithography process can make. Subsequently, a hard mask of half critical dimension is formed in the silicon oxide layer by using the photoresist layer as an etching mask. After the oxide hard mask is formed, the gate structure of half critical dimension is formed by using the oxide hard mask.

Abstract: Structure of a wide voltage operation regime double heterojunction bipolar transistor, specifically a modified InGaP/GaAs double heterojunction bipolar transistor featuring a very broad collector-emitter voltage operation range, an invention of high speed, low power consumption and high breakdown voltage rated microwave power transistor. Unique in the incorporation of In.sub.0.49 Ga.sub.0.51 P collector layer, GaAs delta-doping sheet and undoped GaAs spacer in the collector zone. The introduction of a spacer with a delta doping sheet into the effective base-collector heterojunction serves to eliminate potential spike from appearing at base-collector interfacing any more, thus effectively precludes electron blocking effect. In the emitter zone the inventive design comprises a five-period In.sub.0.49 Ga.sub.0.

Abstract: A method for making improved capacitor bottom electrodes (capacitor nodes) having longer refresh cycle times and increased capacitance for DRAM cells has been achieved. The method involves using a polysilicon high-temperature film (HTF) instead of the conventional doped polysilicon to form the node capacitors. After forming the DRAM pass transistors (FETs) and depositing an insulating layer, node contact openings are etched in the insulator to the drain of the FET. The capacitor bottom electrodes are formed by depositing a polysilicon HTF at a temperature of at least 650.degree. C. using a reactant gas mixture of H.sub.2 /SiH.sub.4 /PH.sub.3, which results in a longer refresh cycle time and increased capacitance. This results in a significantly improved final die yield. After forming an interelectrode dielectric layer on the bottom electrodes, another doped polysilicon layer is deposited to form the top electrodes to complete the DRAM cells.

Abstract: An electrolytic fueling system for engine comprises generally a water tank, an electrolyte, a segregator, an acetone container, an automatic air valve, a pressure control device and a multi-point antibackfire device connected by a number of conduits or passage thereinbetween for producing dried and purified gas of hydrogen and oxygen to run a generic combustion engine. The improvement of this disclosure is characterized in adapting a plurality of cup shaped water absorbing sintered alloy blocks which are of different size and sequentially nested in the electrolyte and interlocked with the anodes and cathodes of the power source. The electrolyte in which the blocks immerse is a mixture of fresh water and potassium hydroxide (KOH) in predetermined proportion.

Abstract: An automobile air conditioning system comprises generally a regenerator, a segregator, a condenser, an evaporator, an absorber, a heat exchanger and a plurality of conduits intercommunicated therein between to form a circulation system producing cooled air. The improvement of this disclosure is characterized with the adaptation of a coil tube wound around the outer periphery of an exhaust pipe and utilizing the residual heat of the waste gas expelled from the engine to vaporize the liquidized refrigerant NH, instead of a compressor. In addition a tubular network is provided to utilize the heat from the sun which is collected on roof and bonnet panels, to strengthen the capability of cooled air production. This invention would release the load of a compressor from the engine and achieve a savings of energy.