Abstract: An electronic device with camera functions includes a housing and a camera module. The housing has a first opening and a second opening. The first opening is disposed on a display surface of the housing, and the second opening is disposed on a rear surface of the housing. The camera module is located between the first opening and the second opening. Therefore, a user can take a photograph for an object by the display surface or the rear surface of the electronic device facing toward the object.

Abstract: A method of manufacturing a semiconductor device, and the method includes forming a stack of a work function layer, a blocking structure, and a metal cap layer sequentially on a substrate. The forming of the blocking structure includes sequentially depositing at least a metal diffusion prevention layer over the work function layer and an electrical performance enhancement layer over the metal diffusion prevention layer before forming the metal cap layer. The electrical performance enhancement layer includes a TiN layer having a Ti/N ratio greater than 1.

Abstract: A method of filling gaps between gates with doped flowable pre-metal dielectric (PMD) and the resulting device are disclosed. Embodiments include forming at least two dummy gates on a substrate, each dummy gate being surrounded by spacers; filling a gap between adjacent spacers of the at least two dummy gates with a flowable PMD; implanting a dopant in the flowable PMD; and annealing the flowable PMD. Doping the flowable PMD prevents erosion of the PMD, thereby providing a voidless gap-fill.

Abstract: An electronic device with camera functions includes a housing and a camera module. The housing has a first opening and a second opening. The first opening is disposed on a display surface of the housing, and the second opening is disposed on a rear surface of the housing. The camera module is located between the first opening and the second opening. Therefore, a user can take a photograph for an object by the display surface or the rear surface of the electronic device facing toward the object.

Abstract: A suitcase includes a main body and a retractable handle assembly mounted on the main body. The handle assembly includes two outer pipes and at least two inner pipes retractably mounted in the outer pipes respectively. Each of the inner pipes and the outer pipes of the handle assembly is made of a plastic pipe which is formed by a primary material and an auxiliary material. The primary material and the auxiliary material are initially mixed and fused, and are then extruded and molded to form the plastic pipe of each of the inner pipes and the outer pipes of the handle assembly. The primary material includes polycarbonate (PC) or polyoxymethylene (POM). The auxiliary material includes fiber. The fiber of the auxiliary material includes glass fiber or carbon fiber.

Abstract: A method of manufacturing a semiconductor device, and the method includes forming a stack of a work function layer, a blocking structure, and a metal cap layer sequentially on a substrate. The forming of the blocking structure includes sequentially depositing at least a metal diffusion prevention layer over the work function layer and an electrical performance enhancement layer over the metal diffusion prevention layer before forming the metal cap layer. The electrical performance enhancement layer includes a TiN layer having a Ti/N ratio greater than 1.

Abstract: A semiconductor device includes a blocking structure between a metal layer and at least one underlying layer. The blocking structure has a first layer configured for preventing diffusion of metal from the metal layer into the at least one underlying layer, and a second layer configured for enhancing electrical performance of the semiconductor device.

Abstract: A structure and method for replacement metal gate technology is provided for use in conjunction with semiconductor fins or other devices. An opening is formed in a dielectric by removing a sacrificial gate material such as polysilicon. The surfaces of the semiconductor fin within which a transistor channel is formed, are exposed in the opening. A replacement metal gate is formed by forming a diffusion barrier layer within the opening and over a gate dielectric material, the diffusion barrier layer formation advantageously followed by an in-situ plasma treatment operation. The treatment operation utilizes at least one of argon and hydrogen and cures surface defects in the diffusion barrier layer enabling the diffusion barrier layer to be formed to a lesser thickness. The treatment operation decreases resistivity, densifies and alters the atomic ratio of the diffusion barrier layer, and is followed by metal deposition.

Abstract: The present invention relates to a filter device, the filter device includes a housing provided with a through-hole; and a filter structure includes a signal line; a wave filter connected to the signal line, the size of the periphery of the wave filter smaller than the diameter of the through-hole; a connecter connected to one end of the signal line and connected electrically with the wave filter; wherein the filter structure is arranged from the outside of the housing through the through-hole correspondingly, so that the signal line and the wave filter are arranged at the inside of the housing and the connecter is fixed at the through-hole. Hence, the filter structure is locked and fixed optionally from the outside or from the inside of the housing to increase the convenience of the whole assembly.

Abstract: The present disclosure provides various methods of fabricating a semiconductor device. A method of fabricating a semiconductor device includes providing a semiconductor substrate and forming a gate structure over the substrate. The gate structure includes a first spacer and a second spacer formed apart from the first spacer. The gate structure also includes a dummy gate formed between the first and second spacers. The method also includes removing a portion of the dummy gate from the gate structure thereby forming a partial trench. Additionally, the method includes removing a portion of the first spacer and a portion of the second spacer adjacent the partial trench thereby forming a widened portion of the partial trench. In addition, the method includes removing a remaining portion of the dummy gate from the gate structure thereby forming a full trench. A high k film and a metal gate are formed in the full trench.

Abstract: A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.

Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

Abstract: In an example embodiment, an EDA program receives input which includes a selection as to an FPGA die and its device package and a selection as to a structured ASIC die and its device package. If the I/O pins on the device package for the FPGA differ from the I/O pins on the device package for the structured ASIC, the EDA program determines a correspondence between the I/O pins on the two device packages (e.g., by identifying the location of the pads for I/O pins on the structured ASIC die and/or creating a virtual structured ASIC device package whose I/O pins are a superset of the I/O pins on the selected structured ASIC device package), which determination includes checking rules for resource assignments. The EDA program then stores the determined correspondence in a device database where the determined correspondence can be accessed by CAD algorithms.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate. A dummy gate is formed over the substrate. A dielectric material is formed around the dummy gate. The dummy gate is then removed to form an opening in the dielectric material. Thereafter, a work function metal layer is formed to partially fill the opening. The remainder of the opening is then filled with a conductive layer using one of a polysilicon substitute method and a spin coating method.

Abstract: A client computer may be configured to perform computer security operation services, such as malicious code scanning and protection against online threats, using one of several remotely located server computers. The client computer may be configured to determine an operational state of the server computers and determine a protection status of the client computer resulting from use of a server computer of a particular operational state. The protection status may have one of at least three levels and indicate vulnerability of the client computer. The client computer may determine the operational state of a server computer based on available bandwidth for network communication between the client computer and the server computer. The client computer may be configured to allow for automatic or manual selection of another server computer when the currently selected server computer results in the client computer having a protection status below a threshold level.

Abstract: A compensation plate used in a film coating device includes a main body defining a plurality of guiding holes, a plurality of moveable blades connected to the main body, and a plurality of connectors. Each of the plurality of moveable blades defines two through holes corresponding to one of the plurality of guiding holes. The plurality of connectors engage in the through holes and the guiding holes, fix each of the plurality of moveable blades to the main body when each of the plurality of connectors is fastened, and slide in each of the plurality of guiding holes with each of the moveable blades when each of the plurality of connectors releases.

Abstract: A semiconductor device includes a blocking structure between a metal layer and at least one underlying layer. The blocking structure has a first layer configured for preventing diffusion of metal from the metal layer into the at least one underlying layer, and a second layer configured for enhancing electrical performance of the semiconductor device.

Abstract: A structure and method for replacement metal gate technology is provided for use in conjunction with semiconductor fins or other devices. An opening is formed in a dielectric by removing a sacrificial gate material such as polysilicon. The surfaces of the semiconductor fin within which a transistor channel is formed, are exposed in the opening. A replacement metal gate is formed by forming a diffusion barrier layer within the opening and over a gate dielectric material, the diffusion barrier layer formation advantageously followed by an in-situ plasma treatment operation. The treatment operation utilizes at least one of argon and hydrogen and cures surface defects in the diffusion barrier layer enabling the diffusion barrier layer to be formed to a lesser thickness. The treatment operation decreases resistivity, densifies and alters the atomic ratio of the diffusion barrier layer, and is followed by metal deposition.

Abstract: A control system is used for maintaining color of a display device, wherein the color is g formed by brightness of a first, second and a third color elements. The first, second and the third color elements have a first brightness, second brightness and a third brightness respectively and a luminance ratio of the first brightness, second brightness and the third brightness. The control system comprises a light-detecting member, a processing unit and a light source driver. The light-detecting member is used for detecting brightness of the first, second and the third color elements. The processing unit is used for calculating a first attenuation brightness of the first color element, second attenuation brightness of the second color element and a third attenuation brightness of the third color element.