Abstract: The power efficiency of a transmitter is optimized through control of a selected aspect of the transmitter, for instance, a parameter of a power amplifier within the transmitter. The control of the aspect is based on a generated indication of desired average transmitted power. Based on this indication, a hardware path produces a first adjustment signal and a software path produces a second adjustment value, where the second adjustment value has been previously determined to correspond to the particular indication of desired average transmitted power through calibration. A difference between a first adjustment value, which is based on the first adjustment signal, and the second adjustment value is used to produce a correction signal, which is used to alter the first adjustment signal and produce a signal to control the selected aspect of the transmitter.

Abstract: An earthquake alarm clock includes a time display device for displaying time with a beeper and a detecting device. The time display device has a guiding member, along which a movable member runs. When an earthquake takes place, the movable member runs along the guiding member and hits the detecting device. The detecting device is electrically connected the beeper to command the beeper broadcasting an alarm when the detecting device is started.

Abstract: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

Abstract: A lighting and flashing Christmas tree structure apparatus employs a low power control circuit to control the flashing sequence of LED light strings, capable of randomly altering distribution of the light strings with free choice of colors. A plug-free magnetic power system supplies electrical power to a cuboidal body where each of the four sides thereon has an electrical power receptacle free for user selection. With a LED device controller, a magnificent blinking is emitting from the LED light source to delight Christmas atmosphere. The electrical power offered by the present invention is limited below 24 V, which is within the safety range of the electrical properties code for body contact, therefore being free of safety concerns.

Abstract: The present invention is to provide a water-and-dust proof structure for a notebook computer heat sink having a chip set and a heat sink module, characterized by comprising (between the chip set and the heat sink module): a separation plate comprising a receptacle having a prescribed hole therein, the separation plate cooperating with a casing of the notebook computer to form a space inside the notebook computer so that the heat sink module and the chip set on the main board of the notebook computer are separatedly located in different spaces inside the notebook computer and closely contact each other through the receptacle of the separation plate; a resilient frame formed to cooperate with the receptacle of the separation plate and having a prescribed hole therein; a resilient piece formed to cooperated with the prescribed hole and having multiple resilient curve portions; and arranging the resilient frame into the receptacle of the separation plate, the heat sink module cooperating with the resilient piece

Abstract: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

Abstract: A lighting and flashing Christmas tree structure apparatus employs a low power control circuit to control the flashing sequence of LED light strings, capable of randomly altering distribution of the light strings with free choice of colors. A plug-free magnetic power system supplies electrical power to a cuboidal body where each of the four sides thereon has an electrical power receptacle free for user selection. With a LED device controller, a magnificent blinking is emitting from the LED light source to delight Christmas atmosphere. The electrical power offered by the present invention is limited below 24 V, which is within the safety range of the electrical properties code for body contact, therefore being free of safety concerns.

Abstract: A method of manufacturing a microelectronic device comprising forming a patterned feature over a substrate and employing a fluorine-containing plasma source to deposit a conformal polymer layer over the patterned feature and the substrate. The polymer layer is etched to expose the patterned feature and a portion of the substrate, thereby forming polymer spacers on opposing sides of the patterned feature.

Abstract: A strained channel NMOS and PMOS device pair including fully silicided gate electrodes and method for forming the same, the method including providing a semiconductor substrate including NMOS and PMOS device regions including respective gate structures including polysilicon gate electrodes; forming recessed regions on either side of a channel region including at least one of the NMOS and PMOS device regions; backfilling portions of the recessed regions with a semiconducting silicon alloy to exert a strain on the channel region; forming offset spacers on either side of the gate structures; thinning the polysilicon gate electrodes to a silicidation thickness to allow full metal silicidation through the silicidation thickness; ion implanting the polysilicon gate electrodes to adjust a work function; and, forming a metal silicide through the silicidation thickness to form metal silicide gate electrodes.

Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Abstract: The present invention is to provide a water-and-dust proof structure for a notebook computer heat sink having a chip set and a heat sink module, characterized by comprising (between the chip set and the heat sink module): a separation plate comprising a receptacle having a prescribed hole therein, the separation plate cooperating with a casing of the notebook computer to form a space inside the notebook computer so that the heat sink module and the chip set on the main board of the notebook computer are separatedly located in different spaces inside the notebook computer and closely contact each other through the receptacle of the separation plate; a resilient frame formed to cooperate with the receptacle of the separation plate and having a prescribed hole therein; a resilient piece formed to cooperated with the prescribed hole and having multiple resilient curve portions; and arranging the resilient frame into the receptacle of the separation plate, the heat sink module cooperating with the resilient piece

Abstract: A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.

Abstract: A method for forming an ultra narrow semiconductive gate structure utilizes a tapered hardmask covered by an oxide liner. The tapered hardmask is formed over the semiconductive gate material by tapered etching. After the tapered hardmask structure is formed over the semiconductive material, an oxide layer is formed over the tapered hardmask. A sequence of highly selective etch operations are carried out to etch uncovered portions of the semiconductive gate material while the portions of the gate material covered by the tapered hardmask and oxide film remain unetched to form ultra narrow gate structures.

Abstract: A strained channel NMOS and PMOS device pair including fully silicided gate electrodes and method for forming the same, the method including providing a semiconductor substrate including NMOS and PMOS device regions including respective gate structures including polysilicon gate electrodes; forming recessed regions on either side of a channel region including at least one of the NMOS and PMOS device regions; backfilling portions of the recessed regions with a semiconducting silicon alloy to exert a strain on the channel region; forming offset spacers on either side of the gate structures; thinning the polysilicon gate electrodes to a silicidation thickness to allow full metal silicidation through the silicidation thickness; ion implanting the polysilicon gate electrodes to adjust a work function; and, forming a metal silicide through the silicidation thickness to form metal silicide gate electrodes.

Abstract: A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.

Abstract: A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The grooves are selectively, and laterally formed in ion implanted veins, which in turn had been placed at various depths in an intrinsic polysilicon layer via a series of ion implantation steps, each performed at a specific implant energy. An isotopic component of the storage node structure, defining dry etch procedure, selectively etches the highly doped, ion implanted veins at a greater rate than the non-ion implanted regions of polysificon, located between the ion implanted veins, resulting in a necked profile, storage node structure, featuring increased surface area as a result of the formation of the lateral grooves.

Abstract: Methods and structures for preventing salicidation are disclosed. A substrate has an gate electrode on it. Spacers are on sidewalls of the gate electrode, exposing a top portion of the gate electrode. A dielectric layer is formed above the spacers, covering the exposed top portion of the gate electrode. Methods and structures for forming source and drain salicidation are disclosed. They further salicidize source and drain regions which are adjacent to the spacers without forming salicidation on the gate electrode while salicidizing the source and drain regions. Methods and structures for forming gate electrode salicidation are also disclosed. They further form another dielectric layer covering the salicidized source and drain regions. A portion of the dielectric layer is removed so as to expose a top surface of the gate electrode. The gate electrode is then salicidized.

Abstract: Abstract of the Disclosure A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portion reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Abstract: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

Abstract: A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.