Patents by Inventor Wen Chan

Wen Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080112162
    Abstract: The present invention discloses a backlight structure having embedded light emitting diodes (LEDs) and a fabrication method thereof. The backlight structure comprises a PCB having a plurality of arc-shaped pits and necessary circuitry implemented thereon; a nanometer-thick gold layer sputtered on surfaces of said PCB and said plurality of arc-shaped pits; and an LED die embedded in each one of said plurality of arc-shaped pits, wherein said LED die is fused and fixed to the center of said arc-shaped pit by high frequency wave; said LED die is covered with a phosphor molding compound made by mixing phosphor and silica gel; and each one of said plurality of arc-shaped pits and its neighboring portion of PCB is covered by a window layer formed by transparent silica gel.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 15, 2008
    Applicant: TOPSON OPTOELECTRONICS SEMI-CONDUCTOR CO., LTD.
    Inventor: Tsung-Wen Chan
  • Patent number: 7354847
    Abstract: A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w1 in the top layer. A pattern transfer through the underlayer is performed with an anisotropic etch based on H2/N2 and SO2 chemistry. The feature formed in the bilayer stack is trimmed by 10 nm or more to a width w2 by a HBr/O2/Cl2 plasma etch. The pattern transfer through an underlying gate layer is performed with a third etch based on HBr/O2/Cl2 chemistry. The underlayer is stripped by an O2 ashing with no damage to the gate electrode. Excellent profile control of the gate electrode is achieved and a larger (w1?w2) is possible than in prior art methods.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: April 8, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Bor-Wen Chan, Yi-Chun Huang, Baw-Ching Perng, Hun-Jan Tao
  • Publication number: 20080068799
    Abstract: A heat sink structure for light-emitting diode (LED) based streetlamps is disclosed, which comprises an upper cover, on which heat sink fins are integrally formed, and a lower cover. The heat energy generated by the LEDs mounted within the upper cover and the lower cover can be removed through the heat sink fins, achieving the effect of rapid removal of the heat energy.
    Type: Application
    Filed: September 14, 2006
    Publication date: March 20, 2008
    Applicant: Topson Optoelectronics Semi-conductor Co., Ltd.
    Inventor: Tsung-Wen Chan
  • Publication number: 20080037279
    Abstract: A tapered prism illumination apparatus for LCD backlight consists of an LCD, a plurality of LEDs and a heat dissipation base. The plurality of LEDs consists of high power LEDs mounted in the back of the LCD, wherein each of the LEDs includes a light emitting point that is packaged exteriorly with a transparent covering body and, on the light emitting path of the LED, a tapered prism is disposed. In the periphery of the LED a thermally conducting substrate is disposed, while the heat dissipation base is mounted in the rear of the LEDs and has reflecting faces in the periphery of each of the LEDs. When light is generated at the light emitting point, it can be projected onto the tapered prism, by which it is bent by 90°, and then projected onto the LCD via the reflecting faces. The heat generated by the high power LEDs is conducted by the thermally conducting substrate to the heat dissipation base to be removed.
    Type: Application
    Filed: August 8, 2006
    Publication date: February 14, 2008
    Inventor: Tsung-Wen Chan
  • Publication number: 20080007951
    Abstract: A LED decorative lighting structure comprises a plurality of LEDS. Each LED has two electric conductor blades which being directly made by cutting down from a strip of the same material. Each of the two conductor blades is equipped with a terminal which further includes a holding strip and an electric conducting strip. The holding strip is for fixing an outer insulation sheath of a conductor by pressing on it; while the conducting strip is for fixing and making connection with the metallic stranded core wires of the conductor. The holding strips and the electric conducting strips in both conductor blades are disposed in different height with each other so as to avoid shortcircuiting by accidental contact. The plurality of LED constructed as such can be arranged in series/parallel connection thereby forming a desired configuration of the LED decorative lighting structure according to the present invention.
    Type: Application
    Filed: July 6, 2006
    Publication date: January 10, 2008
    Inventor: Tsung-Wen Chan
  • Publication number: 20080007962
    Abstract: Disclosed is a LCD back light module structure comprising one or more than one LED arrayed along an electric conducting stick which being equipped with conductor blades on its surface. The conductor blade is used for connecting the conducting stick to a driving circuit. A blind hole is formed on the conducting stick and the light spot of the Led die is buried in the blind hold and the electric connection is extended from the light spot to the adjacent two conductor blades. After being completed connection for each LED die, the epoxy resin is infused around the blind hole to form a transparent lens. The high crowned configuration of the lens enables the LED to uniformly emit the light therefrom therefore each LED forms a uniformly brilliant lighting surface on the LCD back light module structure.
    Type: Application
    Filed: July 6, 2006
    Publication date: January 10, 2008
    Inventor: Tsung-Wen Chan
  • Publication number: 20070296052
    Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.
    Type: Application
    Filed: June 26, 2006
    Publication date: December 27, 2007
    Inventors: Tan-Chen Lee, Bor-Wen Chan
  • Patent number: 7308042
    Abstract: The power efficiency of a transmitter is optimized through control of a selected aspect of the transmitter, for instance, a parameter of a power amplifier within the transmitter. The control of the aspect is based on a generated indication of desired average transmitted power. Based on this indication, a hardware path produces a first adjustment signal and a software path produces a second adjustment value, where the second adjustment value has been previously determined to correspond to the particular indication of desired average transmitted power through calibration. A difference between a first adjustment value, which is based on the first adjustment signal, and the second adjustment value is used to produce a correction signal, which is used to alter the first adjustment signal and produce a signal to control the selected aspect of the transmitter.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: December 11, 2007
    Assignee: Research In Motion Limited
    Inventors: Xin Jin, Qingzhong Jiao, Wen Chan
  • Publication number: 20070279240
    Abstract: An earthquake alarm clock includes a time display device for displaying time with a beeper and a detecting device. The time display device has a guiding member, along which a movable member runs. When an earthquake takes place, the movable member runs along the guiding member and hits the detecting device. The detecting device is electrically connected the beeper to command the beeper broadcasting an alarm when the detecting device is started.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 6, 2007
    Inventors: Shin-Hua CHOW, Chih-Chien You, I-Chuan Hsu, Tien-Chung Hu, I-Huan Shih, Wen-Chan Hsien
  • Publication number: 20070222000
    Abstract: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.
    Type: Application
    Filed: May 31, 2007
    Publication date: September 27, 2007
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bor-Wen Chan, Jyu-Horng Shieh, Hun-Jan Tao
  • Patent number: 7270450
    Abstract: A lighting and flashing Christmas tree structure apparatus employs a low power control circuit to control the flashing sequence of LED light strings, capable of randomly altering distribution of the light strings with free choice of colors. A plug-free magnetic power system supplies electrical power to a cuboidal body where each of the four sides thereon has an electrical power receptacle free for user selection. With a LED device controller, a magnificent blinking is emitting from the LED light source to delight Christmas atmosphere. The electrical power offered by the present invention is limited below 24 V, which is within the safety range of the electrical properties code for body contact, therefore being free of safety concerns.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: September 18, 2007
    Assignee: Topson Optoelectronics Semi-conductor Co. Ltd.
    Inventor: Tsung-Wen Chan
  • Patent number: 7262963
    Abstract: The present invention is to provide a water-and-dust proof structure for a notebook computer heat sink having a chip set and a heat sink module, characterized by comprising (between the chip set and the heat sink module): a separation plate comprising a receptacle having a prescribed hole therein, the separation plate cooperating with a casing of the notebook computer to form a space inside the notebook computer so that the heat sink module and the chip set on the main board of the notebook computer are separatedly located in different spaces inside the notebook computer and closely contact each other through the receptacle of the separation plate; a resilient frame formed to cooperate with the receptacle of the separation plate and having a prescribed hole therein; a resilient piece formed to cooperated with the prescribed hole and having multiple resilient curve portions; and arranging the resilient frame into the receptacle of the separation plate, the heat sink module cooperating with the resilient piece
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: August 28, 2007
    Assignee: Twinhead International Corp.
    Inventors: Wen-Chan Yu, Shu-Shian Liau
  • Patent number: 7241674
    Abstract: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: July 10, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bor-Wen Chan, Jyu-Horng Shieh, Hun-Jan Tao
  • Publication number: 20070147028
    Abstract: A lighting and flashing Christmas tree structure apparatus employs a low power control circuit to control the flashing sequence of LED light strings, capable of randomly altering distribution of the light strings with free choice of colors. A plug-free magnetic power system supplies electrical power to a cuboidal body where each of the four sides thereon has an electrical power receptacle free for user selection. With a LED device controller, a magnificent blinking is emitting from the LED light source to delight Christmas atmosphere. The electrical power offered by the present invention is limited below 24 V, which is within the safety range of the electrical properties code for body contact, therefore being free of safety concerns.
    Type: Application
    Filed: December 22, 2005
    Publication date: June 28, 2007
    Inventor: Tsung-Wen Chan
  • Patent number: 7202172
    Abstract: A method of manufacturing a microelectronic device comprising forming a patterned feature over a substrate and employing a fluorine-containing plasma source to deposit a conformal polymer layer over the patterned feature and the substrate. The polymer layer is etched to expose the patterned feature and a portion of the substrate, thereby forming polymer spacers on opposing sides of the patterned feature.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: April 10, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor-Wen Chan, Yu-I Wang, Han-Jan Tao
  • Patent number: 7195969
    Abstract: A strained channel NMOS and PMOS device pair including fully silicided gate electrodes and method for forming the same, the method including providing a semiconductor substrate including NMOS and PMOS device regions including respective gate structures including polysilicon gate electrodes; forming recessed regions on either side of a channel region including at least one of the NMOS and PMOS device regions; backfilling portions of the recessed regions with a semiconducting silicon alloy to exert a strain on the channel region; forming offset spacers on either side of the gate structures; thinning the polysilicon gate electrodes to a silicidation thickness to allow full metal silicidation through the silicidation thickness; ion implanting the polysilicon gate electrodes to adjust a work function; and, forming a metal silicide through the silicidation thickness to form metal silicide gate electrodes.
    Type: Grant
    Filed: December 31, 2004
    Date of Patent: March 27, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bor-Wen Chan, Yuan-Hung Chiu, Han-Jan Tao
  • Patent number: 7172933
    Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: February 6, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chun Huang, Bow-Wen Chan, Baw-Ching Perng, Lawrence Sheu, Hun-Jan Tao, Chih-Hsin Ko, Chun-Chieh Lin
  • Publication number: 20060262507
    Abstract: The present invention is to provide a water-and-dust proof structure for a notebook computer heat sink having a chip set and a heat sink module, characterized by comprising (between the chip set and the heat sink module): a separation plate comprising a receptacle having a prescribed hole therein, the separation plate cooperating with a casing of the notebook computer to form a space inside the notebook computer so that the heat sink module and the chip set on the main board of the notebook computer are separatedly located in different spaces inside the notebook computer and closely contact each other through the receptacle of the separation plate; a resilient frame formed to cooperate with the receptacle of the separation plate and having a prescribed hole therein; a resilient piece formed to cooperated with the prescribed hole and having multiple resilient curve portions; and arranging the resilient frame into the receptacle of the separation plate, the heat sink module cooperating with the resilient piece
    Type: Application
    Filed: March 21, 2006
    Publication date: November 23, 2006
    Applicant: Twinhead International Corp.
    Inventors: Wen-Chan Yu, Shu-Shian Liau
  • Patent number: 7122484
    Abstract: A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: October 17, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Baw-Ching Perng, Yi-Chen Huang, Jun-Lung Huang, Bor-Wen Chan, Peng-Fu Hsu, Hsin-Ching Shih, Lawrance Hsu, Hun-Jan Tao
  • Patent number: 7081413
    Abstract: A method for forming an ultra narrow semiconductive gate structure utilizes a tapered hardmask covered by an oxide liner. The tapered hardmask is formed over the semiconductive gate material by tapered etching. After the tapered hardmask structure is formed over the semiconductive material, an oxide layer is formed over the tapered hardmask. A sequence of highly selective etch operations are carried out to etch uncovered portions of the semiconductive gate material while the portions of the gate material covered by the tapered hardmask and oxide film remain unetched to form ultra narrow gate structures.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: July 25, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Bor-Wen Chan, Baw-Ching Perng, Ying-Tsung Chen