Abstract: The power efficiency of a transmitter is optimized through control of a selected aspect of the transmitter, for instance, a parameter of a power amplifier within the transmitter. The control of the aspect is based on a generated indication of desired average transmitted power. Based on this indication, a hardware path produces a first adjustment signal and a software path produces a second adjustment value, where the second adjustment value has been previously determined to correspond to the particular indication of desired average transmitted power through calibration. A difference between a first adjustment value, which is based on the first adjustment signal, and the second adjustment value is used to produce a correction signal, which is used to alter the first adjustment signal and produce a signal to control the selected aspect of the transmitter.

Abstract: A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.

Abstract: A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w1 in the top layer. A pattern transfer through the underlayer is performed with an anisotropic etch based on H2/N2 and SO2 chemistry. The feature formed in the bilayer stack is trimmed by 10 nm or more to a width w2 by a HBr/O2/Cl2 plasma etch. The pattern transfer through an underlying gate layer is performed with a third etch based on HBr/O2/Cl2 chemistry. The underlayer is stripped by an O2 ashing with no damage to the gate electrode. Excellent profile control of the gate electrode is achieved and a larger (w1?w2) is possible than in prior art methods.

Abstract: A method for forming an ultra narrow semiconductive gate structure utilizes a tapered hardmask covered by an oxide liner. The tapered hardmask is formed over the semiconductive gate material by tapered etching. After the tapered hardmask structure is formed over the semiconductive material, an oxide layer is formed over the tapered hardmask. A sequence of highly selective etch operations are carried out to etch uncovered portions of the semiconductive gate material while the portions of the gate material covered by the tapered hardmask and oxide film remain unetched to form ultra narrow gate structures.

Abstract: A method of manufacturing a microelectronic device comprising forming a patterned feature over a substrate and employing a fluorine-containing plasma source to deposit a conformal polymer layer over the patterned feature and the substrate. The polymer layer is etched to expose the patterned feature and a portion of the substrate, thereby forming polymer spacers on opposing sides of the patterned feature.

Abstract: A hypocycloid reducing apparatus includes a hollow outside bracket, a hollow inside bracket and a driven input that is rotated by a rotating mechanism, such as a motor. The outside bracket has a passage with N quantity of lobe grooves. The inside is rotatably mounted in the passage of the outside bracket and has an inner space, M quantity of through holes and an output shaft. The through holes are arranged in an annular arrangement, are aligned with the lobe grooves and each through hole holds a roller. The driven input is mounted rotatably in the inner space and has an off-center assembly to encounter sequentially with each roller to actuate rotating the inside bracket. Therefore, a speed of revolution of the rotating mechanism is reduced to the output shaft. A volume of the reducing apparatus is minimized, as is noise produced during operation.

Abstract: A semiconductor device (1) has a fin (2) and a multiple gate electrode (3) over the fin (2), the multiple gate electrode (3) being a layer of gate electrode material with a substantially planar surface (13b) to support a patterned mask (14a), the mask (14a) having a uniform thickness and a planar surface controlling the patterning dimensions of the patterned mask (14a).

Abstract: A plasma etch method for forming a patterned target layer within a microelectrcnic product forms an etch residue layer adjoining a patterned mask layer formed upon a blanket target layer. After removing the patterned mask layer, the etch residue layer is laterally increased to form a laterally increased etch residue layer. The laterally increased etch residue layer is employed as an etch mask for forming the patterned target layer from the blanket target layer. The method is particularly useful for forming gate electrodes within semiconductor products.

Abstract: A method for monitoring plasma parameters during a plasma process such as a plasma etching process, comparing the measured plasma parameters to predetermined parameter specifications, and either terminating the plasma process or modifying the plasma process in progress to re-establish the plasma parameters within the parameter specifications. The plasma parameters may be measured by the self-excited electron resonance spectroscopy (SEEKS) technique or by microwave interferometry.

Abstract: A method is provided for stripping a photoresist with a carbonized crust formed during a high dose ion implant. The method may be performed in any etch tool or asher including those where a plasma is generated with a RF discharge source and bias power and tools with a microwave downstream plasma flow. An ICP plasma source is preferred for generating plasma from a flow of oxygen and one or more CxHyFz gases such as CH3F and CH2F2 where x, y and z are ≧1. A high photoresist removal rate of from 0.2 to 2 microns per minute is achieved while reducing thickness loss in exposed oxide, polysilicon, and silicon layers compared with conventional methods that employ O2 and CMFN gases. For NMOS and PMOS transistors, Idsat and contact junction leakage are improved.

Abstract: A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The grooves are selectively, and laterally formed in ion implanted veins, which in turn had been placed at various depths in an intrinsic polysilicon layer via a series of ion implantation steps, each performed at a specific implant energy. An isotopic component of the storage node structure, defining dry etch procedure, selectively etches the highly doped, ion implanted veins at a greater rate than the non-ion implanted regions of polysificon, located between the ion implanted veins, resulting in a necked profile, storage node structure, featuring increased surface area as a result of the formation of the lateral grooves.

Abstract: A method for forming a patterned target layer from a blanket target layer employs a pair of blanket hard mask layers laminated upon the blanket target layer. A patterned third mask layer is formed thereover. The method also employs four separate etch steps. One etch step is an anisotropic etch step for forming a patterned upper lying hard mask layer from the blanket upper lying hard mask layer. The patterned upper lying hard mask layer is then isotropically etched in a second etch step to form an isotropically etched patterned upper lying hard mask layer. The method is particularly useful for forming gate electrodes of diminished linewidths and enhanced dimensional control within semiconductor products.

Abstract: Method of fabricating LED assembly disclosed herein can provides a string of original colored high intensity LEDS usable for screen displaying or traffic signal lights molded by injecting harmless polyacrylic resin in a short time duration and at low temperature.

Abstract: A method for monitoring plasma parameters during a plasma process such as a plasma etching process, comparing the measured plasma parameters to predetermined parameter specifications, and either terminating the plasma process or modifying the plasma process in progress to re-establish the plasma parameters within the parameter specifications. The plasma parameters may be measured by the self-excited electron resonance spectroscopy (SEEKS) technique or by microwave interferometry.

Abstract: A method of planarizing a polysilicon plug. A dielectric layer has an opening therein. Polysilicon is deposited into the opening to form a polysilicon layer so that the opening is completely filled and the top surface of the dielectric layer is covered. A high molecular weight compound is deposited to form a sacrificial film over the polysilicon layer. An anisotropic etching of the sacrificial film and the polysilicon layer is carried out to remove the sacrificial film and the polysilicon layer outside the opening.

Abstract: A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The grooves are selectively, and laterally formed in ion implanted veins, which in turn had been placed at various depths in an intrinsic polysilicon layer via a series of ion implantation steps, each performed at a specific implant energy. An isotopic component of the storage node structure, defining dry etch procedure, selectively etches the highly doped, ion implanted veins at a greater rate than the non-ion implanted regions of polysilicon, located between the ion implanted veins, resulting in a necked profile, storage node structure, featuring increase surface area as a result of the formation of the lateral grooves.

Abstract: Within a method for fabricating a split gate field effect transistor (FET) device there is employed a two step etch method for forming a floating gate electrode. Within the two step etch method there is employed a patterned first masking layer and a blanket second masking layer to assist in providing the floating gate electrode with a sharply pointed tip within at least either an upper edge of the floating gate electrode or sidewall of the floating gate electrode. The sharply pointed tip provides the split gate field effect transistor (FET) device with enhanced data erasure performance.

Abstract: Within a method for fabricating a split gate field effect transistor (FET) device there is employed a two step etch method for forming a floating gate electrode. Within the two step etch method there is employed a patterned first masking layer and a blanket second masking layer to assist in providing the floating gate electrode with a sharply pointed tip within at least either an upper edge of the floating gate electrode or sidewall of the floating gate electrode. The sharply pointed tip provides the split gate field effect transistor (FET) device with enhanced data erasure performance.

Abstract: A high intensity light source has a LED assembly consisting of red, green and blue three primary colored LEDS enclosed in a globe whose inner wall surface is spray coated with a fluorescent powder for blending the emitted lights from the LEDS into various resultant colored lights by operating a control circuit, and the resultant lights are outputted through all directional refraction of the globe.

Abstract: A method is disclosed for smoothing the top surface of a layer of polysilicon which, as deposited, has a rough top surface due to the formation of polysilicon grains. A polymer, such as CxFyBrz, is deposited using chemical vapor deposition. The polymer layer has a thickness large enough so that the top surface of the polymer is at least a critical distance above the peaks of the grains on the top surface of the layer of polysilicon. The layer of polymer and part of the layer of polysilicon are then etched away using an etch back method which etches the polymer and polysilicon at the same etch rate. This results in a layer of polysilicon having a smooth top surface and the same thickness over the entire layer of polysilicon.