Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

Abstract: A wireless communication system includes a base station, a customer premise equipment (CPE) and a repeater. The repeater includes a down-link circuit and an up-link circuit. The down-link circuit includes a first receiving antenna array and a first transmitting antenna array, and the up-link circuit includes a second receiving antenna array and a second transmitting antenna array. The down-link circuit is separated from the up-link circuit with a first predetermined distance.

Abstract: A method for controlling an antenna array is provided, which includes following steps. Associations with a plurality of mobile devices are established, and at least one characteristic parameter table corresponding to the mobile devices is generated. When a plurality of transmission request signals are received simultaneously and the mobile devices are divided into a user group, a multi-user antenna index of the antenna array is generated based on the at least one characteristic parameter table, and a plurality of data streams corresponding to the mobile devices are transmitted simultaneously through the antenna array. When the transmission request signals are received simultaneously and the mobile devices are not divided into the user group, a single-user antenna index of the antenna array is generated based on the at least one characteristic parameter table, and the data streams corresponding to the mobile devices are transmitted one-by-one through the antenna array.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a first dielectric layer over a substrate and forming a first recess in the first dielectric layer. The method also includes conformally forming a first movable membrane over the first dielectric layer. In addition, the first movable membrane has a first corrugated portion in the first recess. The method further includes forming a second dielectric layer over the first movable membrane and partially removing the substrate, the first dielectric layer, and the second dielectric layer to form a cavity. In addition, the first corrugated portion of the first movable membrane is partially sandwiched between the first dielectric layer and the second dielectric layer.

Abstract: A repeater includes a donor device, a service device, a control board circuit and a processing circuit. The repeater provides beam selection mechanisms applicable to several scenarios for base stations and CPE, in which an adaptive gain control mechanism can be utilized to reduce oscillations in a down-link circuit and an up-link circuit of the control board circuit.

Abstract: A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber and introducing a plasma-forming gas into the PVD chamber. The plasma-forming gas is an oxygen-containing gas. The method also includes applying a radio frequency (RF) power by a power source to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. The metal target is directly electrically coupled to the power source. The method further includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an ultra-high voltage resistor and methods of manufacture. The structure includes at least one resistor coupled to a well of a doped substrate, the at least one resistor being separated vertically from the well by an isolation region with one end of the resistor being attached to an input pad and another end coupled to circuitry.

Abstract: A smart motion detection device with a determining method includes a memory, a processor, and a sensor array coupled to the memory and the processor. An image captured by the sensor array is processed by the processor. The sensor array is adapted to pre-store the image into the memory when the processor is operated in the sleep mode, and the pre-stored image is transmitted to the processor when the processor is operated in the wakeup mode. The sensor array includes a comparator adapted to generate an alarm signal for switching the processor from the sleep mode to the wakeup mode in accordance with a comparison result of the pre-stored image. The determining method includes the processor analyzing images captured by the sensor array when the sensor array is activated to capture the images, and the processor analyzing images pre-stored inside the memory when the sensor array is not activated.

Abstract: A system performance control device is provided. The system performance control device includes a battery and a controller. The controller is coupled to the battery to obtain battery information from the battery. When the controller detects that the battery capacity of the battery is at a first level according to the battery capacity information, the controller adjusts system performance of the system performance control device to a first setting value. When the controller detects that the battery capacity of the battery is at a second level according to the battery capacity information, the controller adjusts the system performance of the system performance control device to a second setting value, wherein the first level is greater than the second level, and the first setting value is higher than the second setting value.

Abstract: In some embodiments, a sensor is provided. The sensor includes a microelectromechanical systems (MEMS) substrate disposed over an integrated chip (IC), where the IC defines a lower portion of a first cavity and a lower portion of a second cavity, and where the first cavity has a first operating pressure different than an operating pressure of the second cavity. A cap substrate is disposed over the MEMS substrate, where a first pair of sidewalls of the cap substrate partially define an upper portion of the first cavity, and a second pair of sidewalls of the cap substrate partially define an upper portion of the second cavity. A sensor area comprising a movable portion of the MEMS substrate and a dummy area comprising a fixed portion of the MEMS substrate are both disposed in the first cavity. A pressure enhancement structure is disposed in the dummy area.

Abstract: The integrated CMOS-MEMS device includes a CMOS structure, a cap structure, and a MEMS structure. The CMOS structure, fabricated on a first substrate, includes at least one conducting layer. The cap structure, including vias passing through the cap structure, has an isolation layer deposited on its first side and has a conductive routing layer deposited on its second side. The MEMS structure is deposited between the first substrate and the cap structure. The integrated CMOS-MEMS device also includes a conductive connector that passes through one of the vias and through an opening in the isolation layer on the cap structure. The conductive connector conductively connects a conductive path in the conductive routing layer on the cap structure with the at least one conducting layer of the CMOS structure.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first through substrate via (TSV) within a first semiconductor substrate. The first semiconductor substrate has a front-side surface and a back-side surface respectively on opposite sides of the first semiconductor substrate. The first semiconductor substrate includes a first doped channel region extending from the front-side surface to the back-side surface. The first through substrate via (TSV) is defined at least by the first doped channel region. A first interconnect structure on the front-side surface of the first semiconductor substrate. The first interconnect structure includes a plurality of first conductive wires and a plurality of first conductive vias, and the first conductive wires and the first conductive vias define a conductive path to the first TSV.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.

Abstract: A method for forming a resistive random access memory includes forming a layer stack, patterning the layer stack to form a plurality of stack structures, forming a protection layer along sidewalls of the plurality of stack structures, forming a first isolation structure between the plurality of stack structures, forming at least one recess in at least one stack structure to define a plurality of filament units, and forming a second isolation structure in the at least one recess. The layer stack includes a bottom electrode and a resistive switching layer on the bottom electrode.

Abstract: A PET synthetic paper is composed of a PET substrate and a soft ink absorbing coating coated on the PET substrate. The soft ink absorbing coating includes an acrylic coating and a polyurethane coating embossed on the acrylic coating. The acrylic coating has excellent printability and the polyurethane coating has velvety-soft tactility.

Abstract: A stretchable modified polyester film, and more particularly to a modified polyester film for in-mold decoration film and having high extensibility, high light transmittance, low shrinkage (high temperature resistance) and the like is provided. The stretchable polyester film is suitable to serve as a stretchable modified polyester film for an in-mold decoration film. The stretchable modified polyester film includes following components: (a) a polyester resin and (b) an acrylic resin.

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region being between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a gate seal spacer on sidewalls of the gate structure, a first portion of the gate seal spacer being on the first portion of the isolation region between the first fin and the second fin, and a source/drain region on the first fin and the second fin adjacent the gate structure.

Abstract: A smart post-it-like system with functional plug is provided, including at least one main body and a smart electronic device, wherein the at least one main body includes a system-on-chip unit, at least one interface circuit, and at least one functional plug. The system-on-chip unit is disposed in the main body. One end of each of the interface circuits is disposed on the main body and connected to the system-on-chip unit, and one end of each of the functional plugs is connected to another end of each of the interface circuits. A smart electronic device is connected to each of the system-on-chip units, wherein the smart electronic device transmits a setting message to one of the system-on-chip units, and one of the system-on-chip units operates the setting message to generate a first operational message to be transmitted to each of the interface circuits.

Abstract: Methods and systems for detecting objects from aerial imagery are disclosed. The method includes obtaining an image of an area, obtaining a plurality of regional aerial images from the image of the area, classifying the plurality of regional aerial images as a first class or a second class by a classifier, wherein: the first class indicates a regional aerial image contains a target object, the second class indicates a regional aerial image does not contain a target object, and the classifier is trained by first and second training data, wherein the first training data include first training images containing target objects, and the second training data include second training images containing target objects obtained by adjusting at least one of brightness, contrast, color saturation, resolution, or a rotation angle of the first training images; and recognizing a target object in a regional aerial image in the first class.

Abstract: A critical conduction mode (CRM) bridgeless PFC system includes a PFC converter connected to an Alternating Current (AC) source, a zero-current detection (ZCD) circuit for detecting a zero-current state of the PFC converter, a zero-voltage switching (ZVS) detection circuit, and a processor. Voltage divider circuits receive a first voltage and a supply voltage from the PFC converter and the AC source. The ZCD circuit receives divided voltages generated by the voltage divider circuits and generates a ZCD signal. The ZCD signal is used by the ZVS detection circuit to generate a ZVS flag, which is used by the processor to control switching of first through fourth transistors of the PFC converter.