Abstract: A display control method and a display system are provided. An image beam from a light-emitting display layer passes through a liquid crystal display layer to provide an image. The method includes: generating a plurality of second display signals respectively correspond to a plurality of subframes of a frame based on a first display signal, wherein the resolution of the second display signals is lower than that of the first display signal; performing brightness compensation on the first display signal to generate a third display signal; driving the light-emitting display layer according to the second display signals to emit the image beam in the corresponding subframe; and driving the liquid crystal display layer based on the third display signal such that a grayscale variation is generated to the image beam after the image beam passes through the liquid crystal display layer.

Abstract: The present invention provides novel pyrazolo[4,3-c]quinoline derivatives exhibiting specifically inhibition activity to microbiota ?-glucuronidase, whereby providing potent activities to prevent chemotherapy-induced diarrhea (CID) of cancers. Therefore, the compounds of the present invention can be used as (1) chemotherapy-adjuvant to prevent chemotherapy-induced diarrhea (CID) and enhance chemotherapeutic efficiency of cancers; (2) health-food supplement to prevent the carcinogens induced colon carcinoma.

Abstract: A method for forming a fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm.

Abstract: Processes for integrating complementary metal-oxide-semiconductor (CMOS) devices with microelectromechanical systems (MEMS) devices are provided. In some embodiments, the MEMS devices are formed on a sacrificial substrate or wafer, the sacrificial substrate or wafer is bonded to a CMOS die or wafer, and the sacrificial substrate or wafer is removed. In other embodiments, the MEMS devices are formed over a sacrificial region of a CMOS die or wafer and the sacrificial region is subsequently removed. Integrated circuit (ICs) resulting from the processes are also provided.

Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate, receiving a heater, receiving an electrode, and receiving a sensing material. The substrate have a first surface, a second surface opposite to the first surface and a plurality of vias extending from the second surface toward the first surface and filled with a conductive or semiconductive material and a first oxide layer, the first oxide layer surrounding the conductive or semiconductive material in the plurality of vias, and a second oxide layer disposed over the first surface and the second surface. The heater is disposed within a membrane over the first surface of the substrate and electrically connected with the substrate. The electrode is over the heater and the membrane; and the sensing material covers a portion of the electrode.

Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.

Abstract: The present disclosure provides a method of manufacturing a gas sensor. The method includes the following operations: a substrate is received; a conductor layer is formed over the substrate; the conductor layer is patterned to form a conductor with a plurality of openings by an etching operation, the openings being arranged in a repeating pattern, a minimal dimension of the opening being about 4 micrometers; and a gas-sensing film is formed over the conductor.

Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.

Abstract: A MEMS microphone includes a substrate having an opening, a first diaphragm, a first backplate, a second diaphragm, and a second backplate. The first diaphragm faces the opening in the substrate. The first backplate includes multiple accommodating-openings and it is spaced apart from the first diaphragm. The second diaphragm joints the first diaphragm together at multiple locations by pillars passing through the accommodating-openings in the first backplate. The first backplate is located between the first diaphragm and the second diaphragm. The second backplate includes at least one vent hole and it is spaced apart from the second diaphragm. The second diaphragm is located between the first backplate and the second backplate.

Abstract: An integrated microphone device is provided. The integrated microphone device includes a substrate, a plate, and a membrane. The substrate includes an aperture allowing acoustic pressure to pass through. The plate is disposed on a side of the substrate. The membrane is disposed between the substrate and the plate and movable relative to the plate as acoustic pressure strikes the membrane. The membrane includes a vent valve having an open area that is variable in response to a change in acoustic pressure.

Abstract: A rotary emulsification device structure includes a housing, a emulsification element and a rotary disk. The housing includes a chamber with a first inlet, a second inlet and an outlet. The emulsification element is disposed in the chamber and divides the chamber into a first space and a second space. The first inlet is disposed to communicate with the first space, and the second inlet and the outlet are disposed to communicate with the second space. The emulsification element includes a plurality of pores communicating with the first space and the second space. The rotary disk is disposed in the second space and rotates in the second space when being driven. The rotary disk includes a plurality of through holes.

Abstract: A method for accessing a physical region page (PRP) list includes obtaining a PRP address of a PRP list, in which the PRP address has M bits; performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain a page base address if the PRP address is within a page boundary; and performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain next PRP address pointer if the PRP address reaches the page boundary. N is an integer, and M is an integer larger than N.

Abstract: The disclosure is directed to a connection re-direction method used by a UE, a connection re-direction method used by a remote access node, a user equipment using the same method, and a remote access node using the same method. In an aspect, the connection re-direction method used by a UE includes receiving a network connection failure indication; and performing a handover procedure based on a pre-configured handover configuration in response to having received the connection failure indication.

Abstract: A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.

Abstract: A MEMS device includes a first layer and a second layer including a same material, a third layer disposed between the first layer and the second layer, a first air gap separating the first layer and the third layer, a second air gap separating the second layer and the third layer, a plurality of first pillars exposed to the first air gap and arranged in contact with the first layer and the third layer, a plurality of second pillars exposed to the second air gap and arranged in contact with the second layer and the third layer.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer.

Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.

Abstract: A liquid crystal display (LCD) panel adapted to alleviate the separation issue between the pixel array substrate and the opposite substrate is provided. The LCD panel includes a pixel array substrate, a first sealant pattern, a liquid crystal layer, a second sealant pattern and an opposite substrate. The pixel array substrate has an active region and a peripheral region surrounding the active region. The first sealant pattern surrounds the active region. The liquid crystal layer is located on the active region and is located inside the first sealant pattern. The second sealant pattern is located outside the first sealant pattern, and the second sealant pattern includes at least one two-dimensional extending structure. The at least one two-dimensional extending structure is located outside a sidewall corresponding to the first sealant pattern, and includes a plurality of turning structures. The opposite substrate faces the pixel array substrate.

Abstract: A manufacturing method of a display device is disclosed. The method includes the following steps. A first substrate having a first region and a second region is provided. A second substrate is disposed on the first substrate. The second substrate is overlapping the first region. At least one drive IC is disposed on the second region. A protection layer is disposed on the second region, The protection layer is disposed enclosing the at least one drive IC. The protection layer has a maximum height larger than a maximum height of the at least one drive IC.