Abstract: The present application provides a upadacitinib salt compound and a preparation method therefor. The salt involved in the method in the present application has an easy preparation operation, a cheap raw material easy to get, and a good purification effect on upadacitinib, and is beneficial to industrial production.

Abstract: A method for providing voice option prompts is provided. The method is used in a switchboard device. The method includes receiving an incoming call from a client device. The method includes transmitting a voice option sound and a voice option prompt to the client device.

Abstract: A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, a select gate, a floating gate, a floating gate cap layer, and an erase gate. The select gate is disposed on the substrate. The floating gate is disposed on the substrate and laterally spaced apart from the select gate, where the floating gate includes top edges forming a closed shape as viewed from a top-down perspective. The floating gate cap layer is disposed on a top surface of the floating gate, where an area of a top surface of the floating gate cap layer is less than an area of a bottom surface of the floating gate. The erase gate is disposed on the floating gate, and one or more of the top edges are covered with the erase gate. A control gate is covered with the erase gate.

Abstract: A method of treating Alzheimer's disease (AD) in a subject includes administering to the subject a therapeutically effective amount of at least one parathyroid hormone type 1 receptor (PTH1R) agonist.

Abstract: This invention describes a packaging structure for roll-type (wound-type) aluminum conductive polymer capacitor element. Two protective substrates are applied to sandwich a roll-type capacitor element in between with an insulating material surrounding the capacitor element also in between the protective substrates. The protective substrates comprise electrically separated anodic conductive pad and cathodic conductive pad on their surfaces. The capacitor element is oriented with its axis perpendicular to the two substrates. The anodic and cathodic leads of the capacitor element pass through the through holes. An anodic external terminal is plated over the anodic conductive pad and a cathodic external terminal is plated over the cathodic conductive pad so that the anodic external terminal is electrically connected to the anodic lead and the cathodic external terminal is electrically connected to the cathodic lead.

Abstract: A stereo image generation method and an electronic apparatus using the same are provided. The stereo image generation method includes the following steps. A two-dimensional (2D) original image corresponding to a first viewing angle is obtained, and a depth map of the 2D original image is estimated. Interpupillary distance information of a user is detected. A pixel shift processing is performed on the 2D original image according to the interpupillary distance information and the depth map to generate a reference image corresponding to a second viewing angle. An image inpainting processing is performed on the reference image to obtain a restored image. The restored image and the 2D original image are merged to generate a stereo image conforming to a stereo image format.

Abstract: A semiconductor device comprises a first conductive feature on a semiconductor substrate, a bottom electrode on the first conductive feature, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A spacer contacts a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode. A conductive feature contacts the top electrode.

Abstract: To increase an overall access speed and a performance of a bus system, in the present disclosure, a master device is designed to use a clock signal with different clock frequencies to address slave devices and read/write data from/to the slave devices. In an address phase, a first operating frequency which the master device can successfully address the slave devices is used as a clock frequency of the clock signal for addressing. In a read/write phase, a minimum one (i.e., a second operating frequency) of multiple working frequencies of the slave devices is used as the clock frequency of the clock signal for reading/writing, wherein the master device is connected to the slave devices via a bus. The working frequency of the slave device means a maximum clock frequency supported by the slave device.

Abstract: The present disclosure provides a gas sensor. The gas sensor includes a substrate, an insulating layer over the substrate, a conductor layer over and in contact with a top surface of the substrate, and a gas sensing film. The conductor layer includes a conductive pattern having a plurality of openings, and the conductive pattern is embedded in the insulating layer. The gas sensing film is formed over a portion of the conductive pattern.

Abstract: A non-volatile memory device includes at least one memory cell including a substrate, an assist gate, a byte select gate, a floating gate, and an upper gate. The substrate includes a first doped region and a second doped region. The assist gate is disposed on the substrate and adjacent to the second doped region. The byte select gate is disposed on the substrate and adjacent to the first doped region. The floating gate is disposed on the substrate and between the assist gate and byte select gate, and the floating gate includes an upper edge higher than top surfaces of the assist gate and the byte select gate. The upper gate covers the assist gate and the floating gate, and the upper gate is spaced apart from the byte select gate. The upper edge of the floating gate is embedded in the upper gate.

Abstract: A manufacturing method is provided. The method includes steps below. Forming bottom electrodes. Blanketly forming a resistance switching layer on the bottom electrodes. Forming a first insulating material layer on the resistance switching layer. Patterning the first insulating material layer to form insulating patterns. Conformally forming a channel layer having a plurality of channel regions on the resistance switching layer and the insulating patterns, wherein the plurality of channel regions are located on the resistance switching layer and cover opposite sides of the insulating patterns. Forming a second electrode material layer on the channel layer. Patterning the second electrode material layer to form top electrodes, each of the top electrodes is located in corresponding to one of the insulating patterns and covers at least two of the plurality of channel regions.

Abstract: The disclosure is directed to a method used by a user equipment for implementing non-terrestrial network (NTN) to terrestrial network (TN) communication and a user equipment using the same method. In one of the exemplary embodiments, the disclosure is directed to a method used by a user equipment for implementing NTN to TN communication. The method would include not limited to: receiving a cell search and measurement configuration from a non-terrestrial network (NTN), the cell search and measurement configuration comprises information of at least one carrier frequency and at least one NTN tracking area (TA) associated with the carrier frequency; initiating a cell search and measurement procedure; and performing the cell search and measurement procedure by applying the cell search and measurement configuration.

Abstract: A multi-channel switch device is provided. The multi-channel switch device includes a first-stage switch circuit, at least one second-stage switch circuit, and multiple third-stage switch circuits. The first-stage switch circuit includes a first common-mode node, a first input/output terminal, and at least one first-stage connection terminal. The second-stage switch circuit includes a second common-mode node, a second-stage transmission terminal, and multiple second-stage connection terminals. Each of the third-stage switch circuits includes a third common-mode node, a third-stage transmission terminal, a reference terminal, and a second input/output terminal. Two of the first input/output terminal and the at least one first-stage connection terminal are connected through the first common-mode node. Two of the second-stage transmission terminal and the second-stage connection terminals are connected through the second common-mode node.

Abstract: This invention describes a packaging structure for roll-type (wound-type) aluminum conductive polymer capacitor element. Two protective substrates are applied to sandwich a roll-type capacitor element in between with an insulating material surrounding the capacitor element also in between the protective substrates. The protective substrates comprise electrically separated anodic conductive pad and cathodic conductive pad on their surfaces and through holes that pass through the conductive pads. The capacitor element is oriented with its axis perpendicular to the two substrates. The anodic and cathodic leads of the capacitor element pass through the through holes. An anodic external terminal is plated over the anodic conductive pad and a cathodic external terminal is plated over the cathodic conductive pad so that the anodic external terminal is electrically connected to the anodic lead and the cathodic external terminal is electrically connected to the cathodic lead.

Abstract: Various embodiments of the present disclosure are directed towards an electronic device that comprises a semiconductor substrate having a first surface opposite a second surface. The semiconductor substrate at least partially defines a cavity. A first microelectromechanical systems (MEMS) device is disposed along the first surface of the semiconductor substrate. The first MEMS device comprises a first backplate and a diaphragm vertically separated from the first backplate. A second MEMS device is disposed along the first surface of the semiconductor substrate. The second MEMS device comprises spring structures and a moveable element. The spring structures are configured to suspend the moveable element in the cavity. A segment of the semiconductor substrate continuously laterally extends from under a sidewall of the first MEMS device to under a sidewall of the second MEMS device.

Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.

Abstract: A black polyester film and a method for manufacturing the same are provided. The black polyester film includes a physically recycled polyester resin and a chemically recycled polyester resin. The physically recycled polyester resin is formed by a plurality of physically recycled polyester chips. The chemically recycled polyester resin is formed by a plurality of chemically recycled polyester chips and mixed with the physically recycled polyester resin. The plurality of chemically recycled polyester chips further include chemically recycled electrostatic pinning polyester chips. The chemically recycled electrostatic pinning polyester chips contain electrostatic pinning additives, and the electrostatic pinning additives are metal salts. Expressed in percent by weight based on a total weight of the polyester film, a content of the electrostatic pinning additives in the polyester film is between 0.005% and 0.1% by weight. The black polyester film further includes a black additive.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate electrode, a gate insulating layer, an active layer, a dielectric layer, a source electrode, and a drain electrode. The gate insulating layer is disposed between the gate electrode and the active layer, the dielectric layer is disposed on a side of the active layer, and the source electrode and the drain electrode pass through the dielectric layer to electrically connect with the active layer, wherein a first contact surface is formed between the source electrode and the active layer, a second contact surface is formed between the drain electrode and the active layer, the first contact surface and the second contact surface are subjected to a plasma treatment or a deposition treatment to form a protective interface layer.

Abstract: A cabinet for electronic components, which is resistant to shocks resulting in deformation of a housing and unsteady leaning of a cabinet casing, includes a cabinet body, a plurality of supporting units, and a plurality of shock-proof units. The plurality of supporting units is disposed on a bottom portion of the cabinet body, and each of the plurality of shock-proof units includes a shock-proof member and a carrier. An end of the shock-proof member rests on the floor or ground, and the other end is connected to the cabinet body. The carrier is connected to the cabinet body and supports the cabinet body, inclination of the cabinet body following heavy jarring and impacts is prevented.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a first dielectric layer formed over the substrate. The semiconductor device structure also includes a first movable membrane formed over the first dielectric layer. In addition, the first movable membrane has a first corrugated portion and a first edge portion connecting to the first corrugated portion. The semiconductor device structure further includes a second dielectric layer formed over the first movable membrane. In addition, the first edge portion is sandwiched between the first dielectric layer and the second dielectric layer, the first corrugated portion is partially sandwiched between the first dielectric layer and the second dielectric layer and is partially exposed by a cavity, and a bottom surface of the first corrugated portion is lower than a bottom surface of the first edge portion.